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Components, Packaging, and Manufacturing Technology, Part C, IEEE Transactions on

Issue 4 • Date Oct. 1998

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Displaying Results 1 - 12 of 12
  • 1998 Author index

    Page(s): 336 - 341
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    Freely Available from IEEE
  • 1998 Subject Index

    Page(s): 338 - 341
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    Freely Available from IEEE
  • The impact of technology scaling on ESD robustness of aluminum and copper interconnects in advanced semiconductor technologies

    Page(s): 265 - 277
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    Electrostatic discharge (ESD) testing results of aluminum (Al) and copper (Cu) interconnect wires and vias for advanced semiconductor technologies demonstrate that interconnects will be a limiting failure mechanism in the future for ESD robustness of semiconductor chips. Comparison of Cu and Al interconnect and vias ESD robustness and failure mechanisms will be shown. Results demonstrate an improvement in the ESD robustness of a Cu-based interconnect system, compared to Al-based interconnects, with an improvement in the critical current density, J crit, in the human body and machine model time regimes View full abstract»

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  • Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

    Page(s): 286 - 294
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    An electrostatic discharge (ESD) evaluation of a silicided 0.25 μm complementary metal-oxide-semiconductor (CMOS) technology is carried out by HEM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices View full abstract»

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  • Use of compliant adhesives in the large area processing of MCM-D substrates

    Page(s): 311 - 316
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    Large area substrate processing is a key solution for improving the productivity of multichip module deposition (MCM-D) technology. This project is focused on high temperature polymeric adhesives for attachment of silicon tiles to suitable pallets to facilitate large area film processing of MCM structures. Current polymeric high temperature adhesives are predominately polyimide-based that are not reworkable, which places an obstacle to remove the coated substrates and to reuse the high cost pallets. However, an approach will be presented in this paper to address this demand by introducing thermally cleavable links in the thermoset polyimide-amide resin. A series of novel reworkable high temperature (in excess of 350-400°C) adhesives have been developed, that can meet the requirements of adhesion, viscosity, thermal stability, and reworkability of the MCM-D production. Furthermore, scanning electron microscopy (SEM) microstructure images are presented for intuitive reworkability analysis View full abstract»

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  • Energy model for end-of-life computer disposition

    Page(s): 295 - 301
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    It has been postulated that recycling end-of-life computers and related components partially offsets the energy requirements of newly manufactured computers. This benefit can arise from (1) refurbishing and reselling components and systems; (2) “cannibalizing” computers of their high-grade parts such as sheet steel and aluminum; (3) primary material source reduction through true recycling of clean and separated metals, plastics, and glass. This research program undertook an effort to study and quantify this hypothesis View full abstract»

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  • Heat-transfer enhancing features for handler tray-type device carriers

    Page(s): 302 - 310
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    Many test handlers process semiconductor devices in trays which must be rapidly heated or cooled by a forced air flow to a desired test temperature and then back to ambient temperature. This paper describes a new design feature for test-handler tray that significantly increases the rate of convective heat transfer to the tray and the devices in the tray. The improved tray incorporates lateral ribs which breakup thermal boundary layers and enhance mixing. This enhanced heat transfer is especially important in new test-in-tray handlers whose operating speeds can be limited by thermal response times View full abstract»

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  • Very fast transmission line pulsing of integrated structures and the charged device model

    Page(s): 278 - 285
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    Transmission line pulsing (TLP) is well-established for the IV-characterization of electrostatic discharge (ESD)-protection elements. There still is a significant gap between the performance of present TLP-systems and the demands of the charged device model (CDM). A very fast, narrow-pulse (>3.5 ns), high-current TLP (VF-TLP) is designed to reduce this gap. It is feasible to study the pulsed breakdown of gate oxides and to determine at least the quasistatic IV-characteristics of input structures. Gate oxide breakdown is monitored within the first 6 ns of stress. Correlation with CDM (noncontact, nonsocketed) tests and socket discharge model [(SDM) formerly socketed CDM] is achieved in terms of the failure signature. However, the failure thresholds of VF-TLP and CDM/SDM do not correlate due to the different current paths. In the CDM, mobile charge is injected into or coming out of one pin until the full device is at same potential. In the SDM, the full test board is charged and discharged across the device. The VF-TLP current flows between the stress pin and a reference pin for the duration of the square pulse View full abstract»

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  • A study of ESD protection devices for input pins. Discharge characteristics of diode, lateral bipolar transistor, and thyristor under MM and HBM tests

    Page(s): 257 - 264
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    We examined various electrostatic discharge (ESD) protection devices for input pins in the case of floating body substrates to discuss optimal structures effective to both of the machine model (MM) and human body model (HBRM) ESD stresses. Because of a small series resistance, we observed oscillation alternating from positive to negative in the current waveforms during MM stress, leading to weak polarity dependence of ESD performance which is inconsistent with the results for HEM tests. As a result, protection devices effective to both HEM and MM should be robust to bipolar stress. As one of the candidates, we propose a combination of PN diode and thyristor View full abstract»

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  • Compression flow modeling of underfill encapsulants for low cost flip-chip assembly

    Page(s): 325 - 335
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    Flip-chip technology represents a rapidly advancing area in commercial electronics. Flip-chip on board (FCOB) technology also called direct chip attach (DCA) involves the direct interconnection of integrated circuits to low cost organic substrates. In order to ensure adequate reliability, these flip-chip assemblies undergo an underfill encapsulation process in which a polymer material is placed between the chip and the substrate. Conventional underfill processing is achieved through chip site to chip site dispensing and underfill flow via capillary action, making it a costly and time consuming process particularly as device sizes increase and standoff gaps decrease. Extensive cost modeling of conventional flip-chip process technology has shown underfill processing, cleaning, and electroplating solder bumps and substrates to be the major cost driving factors. As part of the Low Cost Next Generation Flip-Chip Processing Program, an advanced flip-chip assembly process is being developed. This process eliminates the need for time consuming capillary flow processing using a compression flow technique where the underfill is applied prior to chip placement. The innovative process integrates the chip placement and polymer underfill processes using a compression or squeeze flow technique. It results in significantly lower assembly costs and reduced cycle time. In general, the compression flow of the underfill material governs assembly yield and reliability. This paper focuses on flow simulation studies of the compression flow chip placement process. It represents a fundamental advancement in compression flow simulation of polymers in its successful application to the complex geometries and surface topologies demanded by miniaturized flip-chip assembly. Here a simulation methodology is developed and simulation studies are conducted to characterize the compression flow of the underfill, estimate required chip placement forces, evaluate the effect of underfill geometry, and assess the potential formation of voids. Results yield design guidelines that give insight into process parameters such as the limits on underfill deposition geometry and underfill viscosity and provide an initial process window View full abstract»

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  • Protection of high voltage power and programming pins

    Page(s): 250 - 256
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    Electrostatic discharge (ESD) protection of an integrated circuit's (IC's) high voltage power pins is achieved without damage to thin oxides by dividing the steady-state voltage and arranging weak forward bias of the diodes of a cantilever clamp. Also, Vpp programming pins are protected by cantilever clamps of various kinds, including some which turn on when breakdown is detected and turn off after Vcc is powered up View full abstract»

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  • The behavior of solder pastes in stencil printing with vibrating squeegee

    Page(s): 317 - 324
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    Stencil printing of solder paste with sinusoidally vibrated squeegee is a new technique developed in recent years used for the assembly of printed circuit boards (PCB's) in surface mount technology (SMT). Understanding of the behavior of solder paste under the action of vibrating squeegee is needed to optimize the process parameters. Two vibration experiments on solder paste were conducted. In the first experiment, a prototype of vibrating squeegee system was used to simulate the printing process and in the second experiment paste samples were packed in a cylindrical container which was horizontally vibrated. Experimental results validate the prior theoretical predictions. Suitable ranges of vibration parameters were found View full abstract»

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Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope