By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 1 • Date Jan. 1999

Filter Results

Displaying Results 1 - 8 of 8
  • Guest Editorial

    Publication Year: 1999 , Page(s): 1 - 2
    Save to Project icon | Request Permissions | PDF file iconPDF (57 KB)  
    Freely Available from IEEE
  • Local memory exploration and optimization in embedded systems

    Publication Year: 1999 , Page(s): 3 - 13
    Cited by:  Papers (24)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application specific requirements. We present an analytical strategy for exploring the on-chip memory architecture for a given application, based on a memory performance estimation scheme. The analytical technique has the important advantage of enabling a fast evaluation of candidate memory architectures in the early stages of system design. Many digital signal-processing applications involve array accesses and loop nests that can benefit from such an exploration. Our experiments demonstrate that our estimations closely follow the actual simulated performance at significantly reduced run times View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Constraint analysis for DSP code generation

    Publication Year: 1999 , Page(s): 44 - 57
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    Code generation methods for digital signal processing (DSP) applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of the combination of resource and timing constraints. The analysis identifies implicit sequencing relations between operations in addition to the preceding constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method to obtain high-quality instruction schedules with low register requirements View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the efficiency of formal synthesis-experimental results

    Publication Year: 1999 , Page(s): 25 - 32
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    Formal synthesis has become an interesting alternative to postsynthesis verification. Formal synthesis means integrating formal validation within the synthesis process by performing synthesis via rule applications. The practical applicability of formal synthesis very much depends on the efficiency of the underlying rules. This paper gives a case study about the complexity of formal synthesis programs. Experiments with two realistic-sized benchmark circuits were performed using the formal synthesis system HASH. HASH provides means for representing and transforming circuits in a secure and logically sound manner. Furthermore, arbitrary synthesis procedures can be invoked to achieve high quality of designs. In this paper, the implementation of a formal scheduling step is used to illustrate efficiency considerations related to formal synthesis View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Techniques for minimizing and balancing I/O during functional partitioning

    Publication Year: 1999 , Page(s): 69 - 75
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    Recent work has demonstrated numerous benefits of functionally partitioning a behavioral process into mutually exclusive subprocesses before synthesizing each process into a custom digital-hardware processor. A key problem during partitioning is minimizing the input/output (I/O) pins or wires between processors. The traditional structural partitioning approach is strongly restricted by such I/O. We previously showed that the new approach of functional partitioning eases this restriction. We now demonstrate a further relaxation of the I/O restriction by introducing the FunctionBus interprocessor bus and the port-calling functional transformation. The FunctionBus allows choice of any size for internal I/O by trading off I/O size for performance, while port calling allows distribution of external I/O almost arbitrarily among modules. We describe experiments showing large I/O reductions through these techniques, with only small performance penalties View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hierarchical algorithm partitioning at system level for an improved utilization of memory structures

    Publication Year: 1999 , Page(s): 14 - 24
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    The object of algorithm design in context with a hierarchically structured memory system is a reduction of access cycles to higher memory levels by an increase of data reuse from levels closer to execution units. The object of our approach is to systematically construct an algorithm coding, starting from a weak single assignment form, so that parameters of the algorithm code (number and type of partitions, scheduling orders) can be directly mapped on parameters of the architecture (number of memory levels, size of the memories, input/output access behavior) and vice versa. Target architectures are processors with from one up to a few execution units and with a hierarchically structured memory system. The approach is based on methods derived from the realm of array synthesis and consists of a recursively defined algorithm partitioning. An approach to a quantitative determination of data reuse in recursively partitioned algorithms is given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesizing controllers from real-time specifications

    Publication Year: 1999 , Page(s): 33 - 43
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (432 KB)  

    We present an algorithm for synthesizing real-time controllers specified in a subset of the interval temporal logic duration calculus. The synthesized controllers are given in terms of programmable logic controller (PLC)-automata, which are an abstract description of programs of polling machines. PLC-automata can be implemented directly on PLCs, a special kind of polling real-time controllers that are often used in industry to control production cells and batch processes. We prove the correctness of the algorithm by the duration calculus semantics for PLC-automata. Furthermore, the set of specifications on which the algorithm terminates with a well-formed PLC-automaton coincides with the set of specifications that are implementable in principle. Hence, the algorithm also decides whether a specification given in this subset of the duration calculus is implementable. We demonstrate the behavior of the algorithm by an example and apply the algorithm to the well-known “gasburner” case study View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A new algorithm for elimination of common subexpressions

    Publication Year: 1999 , Page(s): 58 - 68
    Cited by:  Papers (95)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB)  

    The problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization. In a more general form, this is a problem of common subexpression elimination, and as such it also occurs in compiler optimization and many high-level synthesis tasks. An efficient solution of this problem can yield significant improvements in important design parameters like implementation area or power consumption. In this paper, a new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented. The performance of our method is demonstrated primarily on a finite-duration impulse response filter design. The idea is to implement a set of constant multiplications as a set of add-shift operations and to optimize these with respect to the common subexpressions afterwards. We show that the number of add/subtract operations can be reduced significantly this way. The applicability of the presented algorithm to the different high-level synthesis tasks is also indicated. Benchmarks demonstrating the algorithm's efficiency are included as well View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu