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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 1 • Jan. 1999

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Displaying Results 1 - 8 of 8
  • Guest Editorial

    Publication Year: 1999, Page(s):1 - 2
    Request permission for commercial reuse | PDF file iconPDF (57 KB)
    Freely Available from IEEE
  • A new algorithm for elimination of common subexpressions

    Publication Year: 1999, Page(s):58 - 68
    Cited by:  Papers (178)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (380 KB)

    The problem of an efficient hardware implementation of multiplications with one or more constants is encountered in many different digital signal-processing areas, such as image processing or digital filter optimization. In a more general form, this is a problem of common subexpression elimination, and as such it also occurs in compiler optimization and many high-level synthesis tasks. An efficien... View full abstract»

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  • Hierarchical algorithm partitioning at system level for an improved utilization of memory structures

    Publication Year: 1999, Page(s):14 - 24
    Cited by:  Papers (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    The object of algorithm design in context with a hierarchically structured memory system is a reduction of access cycles to higher memory levels by an increase of data reuse from levels closer to execution units. The object of our approach is to systematically construct an algorithm coding, starting from a weak single assignment form, so that parameters of the algorithm code (number and type of pa... View full abstract»

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  • Constraint analysis for DSP code generation

    Publication Year: 1999, Page(s):44 - 57
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    Code generation methods for digital signal processing (DSP) applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of the combination of reso... View full abstract»

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  • Local memory exploration and optimization in embedded systems

    Publication Year: 1999, Page(s):3 - 13
    Cited by:  Papers (34)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application specific requirements. We present an analytical strategy for exploring the on-chip memory architecture for a given application, based on a memory performance estimation scheme. The analytical technique has the important advantage of enabling a fast evaluation of candidate memory archite... View full abstract»

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  • Techniques for minimizing and balancing I/O during functional partitioning

    Publication Year: 1999, Page(s):69 - 75
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    Recent work has demonstrated numerous benefits of functionally partitioning a behavioral process into mutually exclusive subprocesses before synthesizing each process into a custom digital-hardware processor. A key problem during partitioning is minimizing the input/output (I/O) pins or wires between processors. The traditional structural partitioning approach is strongly restricted by such I/O. W... View full abstract»

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  • On the efficiency of formal synthesis-experimental results

    Publication Year: 1999, Page(s):25 - 32
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (176 KB)

    Formal synthesis has become an interesting alternative to postsynthesis verification. Formal synthesis means integrating formal validation within the synthesis process by performing synthesis via rule applications. The practical applicability of formal synthesis very much depends on the efficiency of the underlying rules. This paper gives a case study about the complexity of formal synthesis progr... View full abstract»

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  • Synthesizing controllers from real-time specifications

    Publication Year: 1999, Page(s):33 - 43
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (432 KB)

    We present an algorithm for synthesizing real-time controllers specified in a subset of the interval temporal logic duration calculus. The synthesized controllers are given in terms of programmable logic controller (PLC)-automata, which are an abstract description of programs of polling machines. PLC-automata can be implemented directly on PLCs, a special kind of polling real-time controllers that... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu