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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 11 • Nov 1989

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Displaying Results 1 - 10 of 10
  • Comparisons of quad trees and 4-D trees: new results [VLSI layout]

    Publication Year: 1989, Page(s):1157 - 1164
    Cited by:  Papers (8)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (636 KB)

    A comparison is made between two tree data structures that support region queries for VLSI layout systems. In a previous study, J.B. Rosenberg (ibid., vol.CAD-4, no.1, p.53-67, 1985) demonstrated that four-dimensional trees have a faster speed but use more memory space than quad trees with bisector lists. In this study the authors show that quad trees without bisector lists, for some small thresho... View full abstract»

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  • Routing in general junctions

    Publication Year: 1989, Page(s):1174 - 1184
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (992 KB)

    A junction is a union of channels. The L-, S-, T-, and X-shaped junction routing problems arise while generating a feasible routing order of channels for the building-block layout strategy. The authors present lower and upper bounds on the widths of the channels of general junctions. In addition to the trivial lower bounds provided by the channel densities, they establish nontrivial existential lo... View full abstract»

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  • Decomposition and factorization of sequential finite state machines

    Publication Year: 1989, Page(s):1206 - 1217
    Cited by:  Papers (50)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1136 KB)

    Algorithms are proposed for decomposing a finite-state machine into smaller interacting machines so as to optimize area and performance of the eventual logic implementation. Cascade decomposition algorithms, which decompose a given machine into independent and dependent components, have been proposed in the past. The authors propose a more powerful form of decomposition where both components of th... View full abstract»

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  • Knowledge-based functional specification of test and maintenance programs

    Publication Year: 1989, Page(s):1145 - 1156
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1080 KB)

    An expert system prototype is presented whose aim is to select a test strategy for complex devices, logic PC boards, or systems. Given a set of resources on the board and a set of functions which are performed using these (or a subset of these) resources, the expert system produces a sequence of functions through which the board should be tested. The sequence should be among the best according to ... View full abstract»

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  • Exact algorithms for multilayer topological via minimization

    Publication Year: 1989, Page(s):1165 - 1173
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (748 KB)

    In the past, several heuristic algorithms were developed for the topological via minimization problem. It was very recently shown to be NP-hard even for the two-layer channel routing case with two-terminal nets only. The authors show that if no local net exists in a channel, this problem is solvable in O(kn2) time even for k layers, where n is the number of tw... View full abstract»

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  • Automatic synthesis of asynchronous circuits from high-level specifications

    Publication Year: 1989, Page(s):1185 - 1205
    Cited by:  Papers (118)  |  Patents (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2036 KB)

    The authors construct a processor design approach that does not require the distribution of a clocking signal. To facilitate design of processors that use fully asynchronous components, the first step is to design hazard-free asynchronous interconnection circuits. To this end, a deterministic algorithm was developed to synthesize asynchronous interconnection circuits from high-level specifications... View full abstract»

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  • Performance prediction for adaptive quad tree graphical data structures

    Publication Year: 1989, Page(s):1218 - 1222
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Performance prediction of multiple-storage quad trees is treated. Using random graphical data models, expected values of essential parameters such as the number of internal nodes, the number of object references, and the number of lists are estimated. From these results, more practical characteristics such as memory usage and the speed of windowing operations are obtained. The accuracy of the appr... View full abstract»

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  • Design of multioutput CMOS combinational logic circuits for robust testability

    Publication Year: 1989, Page(s):1222 - 1226
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (484 KB)

    The author proposes a testable design for multioutput functions using parity gates that always produces a realization with robust tests. The use of parity gates allows more logic sharing among various outputs than would have been possible otherwise. The solution presented here has the ability to accommodate any fan-in restriction and grow in number of levels. The new design is well suited for mult... View full abstract»

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  • The Byzantine hardware fault model

    Publication Year: 1989, Page(s):1226 - 1231
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A new fault model for temporary failures is presented. This model is motivated and supported by recent experimental studies on types of temporary failures which cannot be explained by existing models. This new fault is called a Byzantine fault by analogy with the well-known Byzantine Generals problem in distributed systems. An example of an important type of Byzantine fault called a short transien... View full abstract»

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  • An analytical model for the aliasing probability in signature analysis testing

    Publication Year: 1989, Page(s):1133 - 1144
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (832 KB)

    The Markov chain model of linear feedback shift-registers (LFSRs) for signature analysis testing is analytically solved to obtain the exact expression of the aliasing error probability as a function of test length, error probability, and the structure of the feedback network. The dependence on feedback configuration is explored in depth, and it is proven that maximum-length LFSRs have the best per... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu