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Electron Devices, IEEE Transactions on

Issue 1 • Date Jan 1999

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Displaying Results 1 - 25 of 37
  • Rapid thermal anneal of gate oxides for low thermal budget TFT's

    Page(s): 63 - 69
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    The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O2), argon (Ar), and nitrous oxide (N2O) is investigated. Improvement in charge to breakdown (Qbd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N2O and Ar ambients result in higher Qbd compared to O2 ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique View full abstract»

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  • Influence of surface recombination on the burn-in effect in microwave GaInP/GaAs HBT's

    Page(s): 10 - 16
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    In this paper, we report on the early increase of the dc current gain (burn-in effect) due to the electrical stress of carbon doped GaInP/GaAs heterojunction bipolar transistors (HBTs). Devices featuring different passivation layers, base doping, and emitter widths were investigated. The obtained data demonstrate that the burn-in effect is due to a reduction of the surface recombination located at the extrinsic base surface, around the emitter perimeter. It is concluded that the recombination centers are related to defects at the passivation/semiconductor interface and that, during the stress, they are passivated by hydrogen atoms released from C-H complexes View full abstract»

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  • The 1/f noise of InP based 2DEG devices and its dependence on mobility

    Page(s): 194 - 203
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    The 1/f noise of various InP-based two-dimensional electron gas (2DEG) structures with InGaAs channels was investigated at room temperature in the frequency range from 0.4 Hz to 100 kHz. The experimental results on the gate-bias dependent 1/f noise in MBE-grown InAlAs/InGaAs/InP heterostructure field-effect transistors (HFET's) biased in the ohmic region were interpreted in the framework of a model which considers a separation of the HFET into a parasitic and the gated channel region. The results reveal a significant dependence of the Hooge parameter αHg of the gated channel region on the bias dependent mobility μg. The assumed inverse proportionality between αHg and μg due to Coulomb interactions near pinchoff allows an exact description of the noise behavior in the whole bias range. Additionally, the 1/f noise in ungated 2DEG structures of three different MOCVD-grown Al-free and five different MBE-grown Al-containing InP-based heterostructures with InGaAs channels was investigated with respect to the channel design. In spite of various channel designs with mobilities between 6470 cm2/Vs and 11 500 cm2/Vs, the Hooge parameter of all devices showed a clear dependence on mobility (αH-2.6). The lowest observed Hooge parameter αH=1.5×10-5 corresponding to the sample with the highest mobility was attributed to two-dimensional (2-D) phonon scattering processes View full abstract»

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  • Enhancement of high-temperature high-frequency performance of GaAs-based FETs by the high-temperature electronic technique

    Page(s): 24 - 31
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    This paper reports the effects of high temperature on high-frequency/high-speed field effect transistors (FETs), particularly GaAs-based MESFETs and HEMTs. The high-temperature electronic technique (HTET) was employed to stabilize and improve the performance of these devices at high temperatures. This work focuses on detailed high-temperature experiments of high-frequency scattering parameters of various transistors. Comparable gain level to that obtained at room temperature was achieved at elevated temperature through the use of the HTET View full abstract»

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  • Surface-states effects on GaAs FET electrical performance

    Page(s): 214 - 219
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    We analyzed the effects of surface-states on GaAs FET electrical performance with a two-dimensional (2-D) device simulator that used a surface-state model based on Shockley-Read-Hall (SRH) statistics. We found that under typical FET operating conditions, electron-trap-type surface-states pin the surface potential to the electron quasi-Fermi level (that is, the n-type channel potential), whereas hole-trap-type surface-states pin it to the hole quasi-Fermi level (that is, the gate potential). This difference affects both the electric-field distribution along the channel and the drain current values. The transient responses to step-bias application at the gate and at the drain showed slow transients due to the surface-states, but the directions of the shifts were opposite for the different trap-types. We explain these phenomena using a theory based on Shockley-Read-Hall statistics for the surface-states View full abstract»

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  • Analysis of the spurious negative resistance of PN junction avalanche breakdown

    Page(s): 230 - 236
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    The PN junction avalanche breakdown simulation with the local temperature model shows the negative resistance in the current-voltage I-V characteristics in contrast to the simulation with the local field model. We show that the negative resistance is due to the increase of the electron temperature with the reverse current increase near the depletion layer edge where the hot electrons heated in the depletion region are embedded in a large number of cold electrons. It is also shown that the negative resistance predicted by the local temperature model is spurious with the help of Tail Electron HydroDynamic (TEHD) impact ionization model which separately considers the hot carrier population View full abstract»

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  • Design considerations of high-κ gate dielectrics for sub-0.1-μm MOSFET's

    Page(s): 261 - 262
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    The potential impact of high-κ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities. It is shown that the short-channel performance degradation caused by the fringing fields from the gate to the source/drain regions, is mainly determined by the gate thickness-to-length aspect ratio. In addition, the gate stack configuration also plays an important role in the determination of the device short-channel performance degradation View full abstract»

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  • The effect of gate recess profile on device performance of Ga0.51In0.49P/In0.2Ga0.8As doped-channel FET's

    Page(s): 48 - 54
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    The effect of gate recess profile on device performance of Ga0.51In0.49P/In0.2Ga0.8As doped-channel FETs was studied. In the experiment, Ga0.51In 0.49P/In0.2Ga0.8As doped-channel FETs (DCFET's) using triple-recessed gate structure were compared with devices using single-recessed and double-recessed gate structures. It is found that triple-recessed gate approach provides higher breakdown voltage (35 V) than single-recessed (16 V) and double-recessed gate (28 V) approaches. This is attributed to the larger aspect ratio in the triple-recessed gate structure. A unified method to calculate the breakdown voltages of MESFETs, HEMTs and DCFETs (or MISFETs) of any given arbitrary recessed gate profile was proposed and used to explain the experimental results View full abstract»

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  • Three-dimensional DIBL for shallow-trench isolated MOSFET's

    Page(s): 139 - 144
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    This work presents a new phenomenon: the three-dimensional (3-D) DIBL effect. The effect is examined by studying the width-dependent punchthrough leakage of deep-submicron shallow-trench isolated (STI) MOSFET's. Different from previous works on STI, where phenomena are investigated in a low Vd range, the 3-D DIBL is based on analyses in the large Vd range. For STI process,the effect suppress DIBL and the suppression is more effective as scaling down device width. The phenomenon is a result of the 3-D electrostatic effect, which diverts drain fields away from channel into the gate electrode over field oxide region. The effect reduces the total drain fields penetrating through the channel into the source, and hence suppress the DIBL. A simple dipole theory describing the 3-D DIBL phenomenon is presented to extend the previous DIBL theory, which is based on two-dimensional (2-D) approach. Three-dimensional device simulations are used to obtain insights on electric field and surface potential to illustrate the physical basis for the 3-D DIBL theory View full abstract»

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  • Measurement of buried oxide thermal conductivity for accurate electrothermal simulation of SOI device

    Page(s): 251 - 253
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    Finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on insulator (SOI) devices. There is uncertainty about the conductivity of different forms of SiO 2, particularly that of buried oxides. This paper presents a novel approach to measure this conductivity, using structures that are compatible with standard bipolar or CMOS processes. Thermal conductivity values of 0.66 and 0.82 W/mK, respectively, were found for 300-nm BESOI and 420-nm SIMOX oxides at room temperature. The measured variations of thermal conducitivity with temperature agree well with bulk SiO2 behavior. Better agreement between measurement and finite element simulation of MOSFET thermal resistance is obtained by using these extracted thermal conductivity values. It is also shown that the role of the silicon substrate in determining the thermal resistance of the device can be calculated using a simple analytical model. This is important when one wishes to calculate accurately individual thermal resistances of transistors in a given circuit View full abstract»

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  • 2.5 kV-1000 A power pack IGBT (high power flat-packaged NPT type RC-IGBT)

    Page(s): 245 - 250
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    A 2.5 kV-1000 A power pack IGBT (flat-packaged reverse conducting IGBT) has been developed using NPT (non-punchthrough) IGBT chip technology, the gate-source repair technology, the parallel connection technology with no oscillation and the multi-chip assembly technology. The power pack IGBT is specially designed for high power and highly reliable industrial and traction applications. Compared with conventional IGBT modules, this power pack IGBT has high reliability by use of a hermetic package and a press contact structure. In addition to the high reliability, this power pack IGBT is simple and compact for a 2.5 kV-1 kA class device because the assembled IGBT and FWD chips are able to shrink due to the low thermal impedance of both side cooling. The power pack IGBT shows the high blocking voltage of 2.5 kV, the typical saturation voltage of 4.2 V at the collector current (IC ) of 1000 A, the junction temperature (Ti) of 125°C, and the turnoff capability of over 3×IC View full abstract»

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  • 1/f noise in ion sensitive field effect transistors from subthreshold to saturation

    Page(s): 259 - 261
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    The present paper presents extensive measurements of low frequency noise in pH ion sensitive field effect transistors (ISFET's) under various bias conditions corresponding to the gate voltage changing from subthreshold to saturation, in the frequency range between 1 Hz and 100 kHz. The noise measurements were performed in solutions with pH in the range of pH4 to pH10, at room temperature. In contrast to previously reported results, the measured ISFET's exhibit clearly 1/f noise down to 1 Hz View full abstract»

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  • Observation of “capacitance overshoot” in the transient current measurement of polysilicon TFT's

    Page(s): 134 - 138
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    We have observed and analyzed a new effect in the transient current measurement of polysilicon TFT's: the presence of an “overshoot” in the transient response, which implies a time dependent gate capacitance exceeding Cox WL. We have also performed two-dimensional (2-D) transient simulations to explain the experimental results. Our analysis indicates that a TFT circuit model based on lumped intranodal impedances cannot explain the observed transient current behavior. It follows that the “subtransistor” approach is essential for accurate dynamic circuit simulations View full abstract»

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  • Oscillation effects in IGBT's related to negative capacitance phenomena

    Page(s): 237 - 244
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    Insulated gate bipolar transistors (IGBT's) are inherently unstable at high collector voltages due to negative gate capacitance values. We investigate IGBT gate voltage oscillations by experiment and through computer simulation. In addition, we show that under certain gate circuit conditions, gate voltage oscillations can lead to already observed collector current imbalance effects View full abstract»

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  • Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

    Page(s): 173 - 183
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    A whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits is proposed to provide a real whole-chip ESD protection for submicron CMOS IC's without causing unexpected ESD damage in the internal circuits. The efficient VDD-to-VSS ESD clamp circuit has been designed to provide a low-impedance path between the VDD and VSS power lines of the IC during the ESD-stress condition, but this ESD clamp circuit is kept off when the IC is under its normal operating condition. Due to the parasitic resistance and capacitance along the VDD and VSS power lines, the ESD-protection efficiency is dependent on the pin location on a chip. Therefore, an experimental test chip has been designed and fabricated to build up a special ESD design rule for whole-chip ESD protection in a 0.8-μm CMOS technology. This whole-chip ESD protection design has been practically used to rescue a 0.8-μm CMOS IC product with a pin-to-pin HBM ESD level from the original level of 0.5 kV to become above 3 kV View full abstract»

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  • Intersubband optical absorption in strained double barrier quantum well infrared photodetectors

    Page(s): 83 - 88
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    A systematic theoretical investigation of intersubband optical absorption in AlGaAs-AlAs-InGaAs strained double barrier quantum well is presented for the first time. Electron states are calculated within the effective mass approximation which includes the effects of subband nonparabolicity and strain, and found to be in good agreement with experiments. Intersubband optical absorption is investigated using the density matrix formalism with the intrasubband relaxation taken into account. Analytical formulas are given for electron energies, absorption coefficient, and responsivity. Subband nonparabolicity and elastic strain are found to significantly influence both electron states and intersubband optical absorption. The peak absorption wavelength is found to decrease linearly if the In composition is increased, and an approximate formula is given. Electron states and optical absorption are affected by the inner barrier thickness if it is less than 40 Å. The results are useful for design and improvement of the performance of quantum well infrared photodetectors operating in the important wavelength region between 1.5 and 4 μm View full abstract»

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  • The effects of extended heat treatment on Ni induced lateral crystallization of amorphous silicon thin films

    Page(s): 78 - 82
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    The effects of extended heat treatment on the rate of metal induced lateral crystallization (MILC) of amorphous silicon (a-Si) were investigated. Orientation image microscopy and transmission electron microscopy were employed to reveal the crystallinity of the thin film and to measure the MILC length. It was found that for circular Ni disc patterns, the radial dimensions of the resulting MILC rings increased with the radii of the Ni discs. The longest MILC lengths were obtained from straight-edged Ni patterns, which effectively had infinite radii of curvature. The MILC rate decreased upon extended heat treatment. One reason is the continuously changing state of the a-Si during the treatment. An additional reason could be the diminishing supply of Ni from the Ni covered area. The contribution of both to the reduction of the MILC rate is discussed View full abstract»

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  • A 63-170 GHz second-harmonic operation of an InP transferred electron device

    Page(s): 17 - 23
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    Theoretical and experimental analysis of a second-harmonic InP transferred electron device is presented for the 63-170 GHz frequency band. This broadband device produces 30 mW at 63 GHz, 85 mW at 122 GHz, and 8 mW at 170 GHz; in all cases the diode is operating in the second-harmonic mode. A continuously-tunable cavity has been used to produce 30-40 mW of output power over the 119-147.5 GHz range without any detectable frequency jumps or power dips. High frequency structure simulator (HFSS) and drift-diffusion harmonic-balance analysis (DDHB) are used to self-consistently analyze the second-harmonic TEO operation. Numerical simulation results are presented that explain the broadband behavior of the device, and determine the optimal device embedding impedance. Simulations are capable of predicting operating frequencies to within several GHz and output powers to within about 20% accuracy View full abstract»

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  • A new soft breakdown model for thin thermal SiO2 films under constant current stress

    Page(s): 159 - 164
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    Soft breakdown properties of thin gate oxide films are investigated using a constant current stress measurement. The soft breakdown can be classified into two different modes from the current conduction characteristics of post breakdown oxides: one of the modes shows a telegraph switching pattern and the other random noise. The generation probabilities of two soft breakdown modes and hard breakdown strongly depend on the stress current. Time-to-breakdown is well characterized by a universal function of stress conditions regardless of the breakdown modes. These experimental findings imply that all types of breakdown originate from the same precursor and the magnitude of the following local heating due to the transient current in a conductive micro spot determines the charge conduction properties after a breakdown event View full abstract»

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  • A modified lucky electron model for impact ionization rate in NMOSFET's at 77 K

    Page(s): 263 - 266
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    The nonstationary effects of electrons at 77 K, in the high field saturation region of the MOSFET, are modeled by incorporating an appropriate electron temperature decrease (-ΔTe) to the carrier energy, within the framework of a modified lucky electron model. For a thin oxide MOSFET (Tcx=5 nm, L0=0.5 μm), ΔTc is a function of the electric field in the saturation region, and increases rapidly with drain bias. However, for a thick oxide MOSFET (Tcx=12.5 nm, Lg=5 μm), ΔTe=280 K is found to adequately describe the impact ionization rate. Our model also explains the crossover of the ionization rates in the thick oxide MOSFET at 77 K and 300 K View full abstract»

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  • Temperature-dependent kink effect model for partially-depleted SOI NMOS devices

    Page(s): 254 - 258
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    This paper reports a closed-form analytical temperature-dependent kink effect model for the partially-depleted SOI NMOS devices. Based on the body-emitter voltage model, an analytical triggering VDS formula for temperature-dependent kink effect has been obtained. According to the analytical model, at a higher operation temperature and with a lighter thin-film doping density, the onset of the kink effect occurs at a larger VDS View full abstract»

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  • A new and flexible scheme for hot-electron programming of nonvolatile memory cells

    Page(s): 125 - 133
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    A new hot electron writing scheme for flash EEPROMs is proposed that combines a positive source to bulk voltage and a ramped voltage on the control gate. The scheme exploits the equilibrium between hot electron injection and displacement current at the floating gate electrode in order to achieve a transient regime where the drain current of the cell is virtually constant. The new method allows one to accurately control the threshold voltage and the programming drain current that is essentially determined by the slope of the control gate ramp and can thus be traded off with programming time over a wide range of values. The main features of the new scheme are experimentally demonstrated on up-to-date 0.6 μm stacked gate flash EEPROM devices View full abstract»

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  • A monolithically integrated three-axis accelerometer using CMOS compatible stress-sensitive differential amplifiers

    Page(s): 109 - 116
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    In this paper, the development of a bulk-micromachined CMOS integrated three-axis accelerometer which includes analog signal conditioning circuits is presented. The accelerometer was designed to simplify the signal processing tasks by incorporating a set of circuits for three-axis signal conditioning. This approach resulted in a 25% reduction of the circuit area. Stress-sensitive differential amplifiers (SSDAs) have been used as signal transducers, because they can be conveniently formed in a small area. The sensitivity and resolution of the fabricated devices realized in 8×8 mm2 die area were 192 mV/g and 0.024 g for Z-axis acceleration, and 23 mV/g and 0.23 g for X and Y axis acceleration, respectively. The electrical noise component in the analog CMOS circuits was reduced by using a chopper stabilization technique. It was observed that there is a proper chopping clock frequency range to maximize the noise reduction effect. The noise of the SSDA was found to be related with the characteristics of CMOS differential amplifiers used. Typical temperature coefficient of sensitivity was about -2000 ppm/°C, which could be reduced to -320 ppm/°C or less by selecting a proper bias condition View full abstract»

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  • Substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel SOI MOSFET's

    Page(s): 151 - 158
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    The substrate-bias effect and source-drain breakdown characteristics in body-tied short-channel silicon-on-insulator metal oxide semiconductor field effect transistors (SOI MOSFET's) were investigated. Here, “substrate bias” is the body bias in the SOI MOSFET itself. It was found that the transistor body becomes fully depleted and the transistor is released from the substrate-bias effect, when the body is reverse-biased. Moreover, it was found that the source-drain breakdown voltage for reverse-bias is as high as that for zero-bias. This phenomenon was analyzed using a three-dimensional (3-D) device simulation considering the body-tied SOI MOSFET structure in which the body potential is fixed from the side of the transistor. This analysis revealed that holes which are generated in the transistor are effectively pulled out to the body electrode, and the body potential for reverse-bias remains lower than that for zero-bias, and therefore, the source-drain breakdown characteristics does not deteriorate for reverse-bias. Further, the influence of this effect upon circuit operation was investigated. The body-tied configuration of SOI devices is very effective in exploiting merits of SOI and in suppressing the floating body-effect, and is revealed to be one of the most promising candidates for random logic circuits such as gate arrays and application specific integrated circuits View full abstract»

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  • Constant-resistance deep-level transient spectroscopy in Si and Ge JFET's

    Page(s): 204 - 213
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    The recently introduced constant-resistance deep-level transient spectroscopy (CR-DLTS) was successfully applied to study virgin and radiation-damaged junction field-effect transistors (JFET's). We have studied three groups of devices: commercially available discrete silicon JFET's; virgin and exposed to high-level neutron radiation silicon JFET's, custom-made by using a monolithic technology; and commercially available discrete germanium p-channel JFET's. CR-DLTS is similar to both the conductance DLTS and to the constant-capacitance variation (CC-DLTS). Unlike the conductance and current DLTS, it is independent of the transistor size and does not require simultaneous measurement of the transconductance or the free-carrier mobility for calculation of the trap concentration. Compared to the CC-DLTS, it measures only the traps inside the gate-controlled part of the space charge region. Comparisons have also been made with the CC-DLTS and standard capacitance DLTS. In addition, possibilities for defect profiling in the channel have been demonstrated. CR-DLTS was found to be a simple, very sensitive, and device area-independent technique which is well suited for measurement of a wide range of deep level concentrations in transistors View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology