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Design & Test of Computers, IEEE

Issue 4 • Date Oct.-Dec. 1998

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Displaying Results 1 - 13 of 13
  • Online VLSI Testing

    Publication Year: 1998, Page(s):12 - 16
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (85 KB)

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  • A D&T Roundtable Deep-Submicron Noise

    Publication Year: 1998, Page(s):82 - 88
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    Freely Available from IEEE
  • Author index

    Publication Year: 1998, Page(s):89 - 90
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    Freely Available from IEEE
  • Subject index

    Publication Year: 1998, Page(s):90 - 92
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    Freely Available from IEEE
  • On-chip IDDQ testing in the AE11 fail-stop controller

    Publication Year: 1998, Page(s):57 - 65
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (316 KB)

    Targeted for safety-critical applications, this microcontroller replaces the classic two-controller safety structure with a single controller containing various online fault detection measures. To minimize chip area without reducing safety, the developers incorporated a combination of concurrent checking, BIST, and IDDQ testing-and considerably extended the standard cell-based design fl... View full abstract»

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  • Online BIST for embedded systems

    Publication Year: 1998, Page(s):17 - 24
    Cited by:  Papers (45)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    Embedded systems must meet increasingly high expectations of safety and high reliability. The authors survey online-testing techniques for identifying faults that can lead to system failure. They focus on online built-in self-test and its role in a comprehensive testing approach View full abstract»

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  • Efficient self-recovering ASIC design

    Publication Year: 1998, Page(s):25 - 35
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    The authors present a framework for tailoring fault-tolerant approaches for both permanent and transient faults to the specific needs of an application. These methodologies provide an efficient alternative to traditional triplication and rollback schemes and allow tailoring of area-resiliency trade-offs for individual designs View full abstract»

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  • Online current testing

    Publication Year: 1998, Page(s):49 - 56
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    Testing professionals must choose the online VLSI testing technique most suitable for mission goals with respect to design complexity, fault coverage, safety level, and product value. Online current testing techniques provide potential solutions to reliability problems in a wide spectrum of fault-tolerant applications View full abstract»

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  • Concurrent checking of clock signal correctness

    Publication Year: 1998, Page(s):42 - 48
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    Traditional concurrent-checking techniques may not detect the occurrence of the transient faults and resulting errors likely to affect clock signals in VLSI systems. The authors present a new method and self-checking circuit implementation for concurrently checking the correctness of clock distribution network signals in synchronous systems View full abstract»

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  • Using laser defect avoidance to build large-area FPGAs

    Publication Year: 1998, Page(s):75 - 81
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    Wafer-scale techniques of defect avoidance expend the complexity limits of field-programmable gate arrays by routing around flawed blocks to build working systems. Experiments on test FPGAs show that laser defect avoidance produces signal delays half those of active switches View full abstract»

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  • Synthesizing fast, online-testable control units

    Publication Year: 1998, Page(s):36 - 41
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (100 KB)

    The authors present the self-checking bypass pipeline, an online-testable controller structure for data-dominated applications. For most circuits in a standard benchmark set, this structure leads to a performance improvement of more than 30% with an area overhead less than 15% that of conventional online-testable finite-state machines View full abstract»

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  • The third millennium's test dilemma

    Publication Year: 1998, Page(s):7 - 11
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (48 KB)

    The president and CEO of Credence Systems, Bill Bottoms, addressed the VLSI test symposium held last April in Monterey, California. His keynote covered some of the challenges test engineers must face in the future. Specifically, Bottoms focused on what's driving the increase in test cost and what the industry can do about it View full abstract»

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  • Fault analysis for networks with concurrent error detection

    Publication Year: 1998, Page(s):66 - 74
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (132 KB)

    The authors propose an approach for fault analysis and simulation of networks designed to have concurrent detection properties. The analysis characterizes all faults that may affect a device and determines the coverage, extracting test vectors and other parameters for evaluating device quality View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty