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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 1998

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Displaying Results 1 - 23 of 23
  • Author index

    Page(s): 1 - 16
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    Freely Available from IEEE
  • Enhancement-mode high electron mobility transistors (E-HEMTs) lattice-matched to InP

    Page(s): 2422 - 2429
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    The fabrication and characterization of high-speed enhancement-mode InAlAs/InGaAs/InP high electron mobility transistors (E-HEMTs) have been performed. The E-HEMT devices were made using a buried-Pt gate technology. Following a Pt/Ti/Pt/Au gate metal deposition, the devices were annealed in a nitrogen ambient, causing the bottom Pt layer to sink toward the channel. This penetration results in a positive shift in threshold voltage. The dc and RF performance of the devices has been investigated before and after the gate annealing process. In addition, the effect of the Pt penetration was investigated by fabricating two sets of devices, one with 25 nm of Pt as the bottom layer and the other with a 5.0 nm bottom Pt layer. E-HEMTs were fabricated with gate lengths ranging from 0.3 to 1.0 μm. A maximum extrinsic transconductance (gmext) of 701 mS/mm and a threshold voltage (VT) of 167 mV was measured for 0.3 μm gate length E-HEMTs. In addition, these same devices demonstrated excellent subthreshold characteristics as well as large off-state breakdown voltages of 12.5 V. A unity current-gain cutoff frequency (f t) of 116 GHz was measured as well as a maximum frequency of oscillation (fmax) of 229 GHz for 0.3 μm gate-length E-HEMTs View full abstract»

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  • Quantifying neutral base recombination and the effects of collector-base junction traps in UHV/CVD SiGe HBTs

    Page(s): 2499 - 2504
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    This work quantifies neutral base recombination in UHV/CVD SiGe heterojunction bipolar transistors (HBTs) using calibrated two-dimensional (2-D) simulation. The simulated collector-base conductance through neutral base recombination (NBR) modulation is far below the experimentally observed values, and hence does not explain the measured output resistance degradation under forced-IB operation. In spite of the output resistance degradation, these UHV/CVD SiGe HBTs have approximately the same base current as the silicon control, and hence higher current gain. Based on the observation of the majority carrier concentration limited recombination in the CB junction depletion layer, as opposed to the minority carrier concentration limited recombination in the neutral base, local presence of traps in the CB junction depletion layer is suggested. This explains the measured CB conductance modulation and the related output resistance degradation without compromising the current gain. Numerical simulations using traps locally introduced into the CB junctions successfully reproduced the measured collector-base conductance from simulation without appreciable degradation in current gain View full abstract»

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  • Low-frequency drain current noise behavior of InP based MODFET's in the linear and saturation regime

    Page(s): 2475 - 2482
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    This paper describes a detailed experimental study of the low-frequency (LF) drain current noise behavior of InP based MODFET's in a broad operation regime, spanning both linear and saturation operation. The noise power spectral density SlD of the predominantly 1/f noise is studied as a function of the gate and drain bias. The experimental noise behavior is compared with available analytical models. It is shown that there is a reasonable agreement between the data and the theoretical models in linear operation. However, no accurate theory exists for the saturation regime. Therefore, an empirical analytical description is proposed, which provides a good approximation for the measurement data base. Furthermore, it can be used as a starting point for phase noise simulations in high-frequency nonlinear circuits View full abstract»

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  • Bulk defect induced low-frequency noise in n+-p silicon diodes

    Page(s): 2528 - 2536
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    The low-frequency 1/f-like noise of gated n+-p silicon diodes has been measured and analyzed in terms of trapping and detrapping of holes in defect centers located in the bulk section of the space charge region at 0.43 eV below the conduction band. Both the trap characteristics and their precise physical location are resolved from the noise measurements showing that the noise producing defect region moves closer to the metallurgical junction when forward bias is increased. The noise measurements independently confirm that thermal substrate pretreatments lower the defect density in the diodes fabricated in Czochralski (CZ) grown substrates. The defect centers are assumed to be associated with precipitated oxygen/dislocation complexes View full abstract»

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  • Device parameter optimization of strained Si channel SiGe/Si n-MODFET's using a one-dimensional charge control model

    Page(s): 2430 - 2436
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    We have simulated the strained Si channel SiGe n-MODFET structure using a one-dimensional (1-D) self-consistent Schroedinger-Poisson charge control model. The quantum confinement effect has been investigated and key transistor parameters have been optimized for maximum fT. It has been found that the doping concentration into the donor layer and the Ge mole fraction of the SiGe layers should be as high as possible, provided that the doping diffusion and the avalanche breakdown are under control and the crystalline quality of the epilayers is not significantly degraded. The optimum channel thickness was found to be between 5 and 7.5 nm. In addition, it has been shown that the thickness of the donor layer should be used for threshold voltage adjustment rather than for fT improvement View full abstract»

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  • A degenerately-doped GaAs Schottky diode model applicable for terahertz frequency regime operation

    Page(s): 2521 - 2527
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    This paper investigates the physics and operation of GaAs Schottky diodes within the terahertz frequency regime. Specifically, electron scattering and transport models are developed for the degenerately doped conditions necessary for very-high-frequency diode operation. This study incorporates the physical effects of electron-electron scattering and degenerate electron statistics into the scattering models for ionized impurities and polar optical phonons. These derivations are then used to arrive at analytical mobility models for transport in degenerate GaAs bulk regions. This work also derives improved expressions for thermionic and field emission within degenerate Schottky barrier structures. These emission models are then combined with a momentum-balance description of electron transport in the bulk region to model the dynamic operation of the diode. Numerical simulation results are presented to illustrate the roles played by thermal emission over the barrier and field (tunneling) emission through the barrier on diode operation at terahertz frequencies. These results clearly demonstrate the strong influence that doping has on the emission currents within heavily doped Schottky diodes View full abstract»

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  • Random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFET's: A 3-D “atomistic” simulation study

    Page(s): 2505 - 2513
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    A three-dimensional (3-D) “atomistic” simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 μm MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position View full abstract»

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  • Design methodology and optimization of gate-driven NMOS ESD protection circuits in submicron CMOS processes

    Page(s): 2448 - 2456
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    This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work View full abstract»

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  • A compact LDD MOSFET I-V model based on nonpinned surface potential

    Page(s): 2489 - 2498
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    Based on nonpinned surface potential concept, in this paper we present a compact single-piece and complete I-V model for submicron lightly-doped drain (LDD) MOSFETs. The physics-based and analytical model was developed using the drift-diffusion equation and based on the quasi two-dimensional (2-D) Poisson equation. The important short-channel device features: drain-induced-barrier-lowering (DIBL), channel-length modulation (CLM), velocity saturation, and the parasitic series source and drain resistances have been included in the model in a physically consistent manner. In this model, the LDD region is treated as a bias-dependent series resistance, and the drain-voltage drop across the LDD region has been considered in modeling the DIBL effect. This model is smoothly-continuous, valid in all regions of operation and suitable for efficient circuit simulation. The accuracy of the model has been checked by comparing the calculated drain current, conductance and transconductance with the experimental data View full abstract»

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  • A high-performance polycrystalline silicon thin film transistor with a silicon nitride gate insulator

    Page(s): 2548 - 2551
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    We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiNx ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiNx and laser annealed poly-Si. After patterning thin a-Si:H/SiNx layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n+ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm2/Vs and a threshold voltage of 1 V View full abstract»

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  • Analysis of Si:Ge heterojunction integrated injection logic (I2L) structures using a stored charge model

    Page(s): 2437 - 2447
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    A quasi-two-dimensional stored charge model is developed as an aid to the optimization of SiGe integrated injection logic (I2L) circuits. The model is structure-based and partitions the stored charge between the different regions of the I2L gate. Both the NpN switching transistor and the PNp load transistor are correctly modeled and the effects of series resistances on the gate operation are taken into account. The model is applied to surface-fed and substrate-fed variants of SiGe I2L and the Ge and doping concentrations varied to determine the important tradeoffs in the gate design. At low injector currents, the substrate-fed variant is found to be faster because of lower values of critical depletion capacitances. At high injector currents, the performance of both variants is limited by series resistances, particularly in the NPN emitter layer. The inclusion of 16% Ge in the substrate-fed I2L gate leads to a decrease in the dominant stored charge by a factor of more than ten, which suggests that gate delays well below 100 ps should be achievable in SiGe I2L even at a geometry of 3 μm. The model is applied to a realistic, self-aligned structure and a delay of 34 ps is predicted. It is expected that this performance can be improved with a fully optimized, scaled structure View full abstract»

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  • Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors

    Page(s): 2514 - 2520
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    The authors report the characterization and analysis of a novel double-gate elevated-channel thin-film transistor (ECTFT) fabricated using polycrystalline silicon. The transistor has a thin channel and thick source/drain regions with a double-gate control. Using this structure, the kink effect in the I-V characteristics of a conventional TFT is completely eliminated, and leakage current at zero gate bias is reduced by over 15 times. The elimination of the kink effect and the significant reduction in leakage current are obtained due to the reduction in lateral electric field at the channel/drain junction region. Two-dimensional (2-D) device simulations are used to study the electric field reduction mechanism in the structure. Experimental results on the forward conduction and gate transfer characteristics of the structure are also presented View full abstract»

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  • IGBT dynamics for clamped inductive switching

    Page(s): 2537 - 2545
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    Clamped inductive switching performance of insulated gate bipolar transistors (IGBTs) have been studied in detail with the aid of extensive measurements and numerical simulations. Internal dynamics of a latch-up free punch-through IGBT during clamped inductive switching is studied using two-dimensional (2-D) mixed device and circuit simulations incorporating the self-heating mechanism. Failure of IGBT during inductive load turn-off is shown to occur due to thermally assisted carrier multiplication at the reverse biased p-base n-drift region junction under the emitter contact View full abstract»

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  • A novel hetero-material gate (HMG) MOSFET for deep-submicron ULSI technology

    Page(s): 2546 - 2548
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    A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 μm technologies View full abstract»

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  • Interfacial gate resistance in Schottky-barrier-gate field-effect transistors

    Page(s): 2407 - 2416
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    We discuss in depth a previously overlooked component in the gate resistance Rg of Schottky-Barrier-Gate FETs, in particular, 0.1-μm gate-length AlInAs/GaInAs MODFETs. The high-frequency noise and power gain of these FETs depend critically on Rg. This has been the motivation for the development of T-gates that keep the gate finger metallization resistance Rga (proportional to the gate width Wg) low, even for very short gate length Lg . Rga increases with frequency due to the skin effect, but our three-dimensional (3-D) numerical modeling shows conclusively that this effect is negligible. We show that the always “larger-than-expected” Rg is instead caused by a component Rgi that scales inversely with Wg. We interpret Rgi as a metal-semiconductor interfacial gate resistance. The dominance of Rgi profoundly affects device optimization and model scaling. For GaAs and InP-based SBGFETs, there appears to exist a smallest practically achievable normalized interfacial gate resistance rgi on the order of 10-7 Ω cm2 View full abstract»

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  • A C-switch cell for low-voltage and high-density SRAMs

    Page(s): 2483 - 2488
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    We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of μA order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 μm design rules View full abstract»

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  • Low-frequency noise of InP/InGaAs heterojunction bipolar transistors

    Page(s): 2400 - 2406
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    The equivalent base noise SIb of InP/InGaAs heterojunction bipolar transistors (HBT's) with a circular pattern emitter is investigated experimentally at a low frequency ranging from 10-105 Hz. The measured SIb exhibits the 1/f dependence in an overall frequency range without any accompanying burst noise. Furthermore, SIb varies as Ibγ for the base current Ib and as d-2 for the emitter diameter d, where the value of γ ranges from 1.62-1.72 depending on d of HBT's used. The 1/f noise model, which rigorously deals with the recombination current at the base surface Ibs as a function of Ib as well as of d is proposed. Applying our noise model to the dependence of SIb on Ib, as well as on d, reveals that even though γ is less than two, the origin of SIb is due to the recombination of electrons at the exposed base surface near the emitter edges. On the basis of theoretical considerations for the diffusion length of electrons and traps at the base surface, the Hooge parameter αH for the noise due to the base surface recombination is deduced to be in the order of 10 -2 for the first time View full abstract»

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  • Emitter series resistance from open-collector measurements-influence of the collector region and the parasitic pnp transistor

    Page(s): 2457 - 2465
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    The open-collector method for determination of the emitter series resistance in integrated bipolar transistors is analyzed. Existing models do not provide the accuracy required for a correct determination of the emitter series resistance. In order to accurately describe the saturation voltage, a set of model equations is derived that provides a more accurate description of the epitaxial collector region. The measured VCE(IE) characteristic is found to depend on the properties of the collector region as well as the parasitic substrate transistor. Using the model developed, a consistent description of measurement results for different bias conditions of the collector-substrate junction is possible. With this new understanding of the open-collector method, an improved procedure to extract the emitter resistance from measurement data is developed, and results of the method applied to integrated bipolar transistors are presented View full abstract»

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  • Read-disturb and endurance of SSI-flash E2PROM devices at high operating temperatures

    Page(s): 2466 - 2474
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    The high-temperature (T) reliability behavior of merged-transistor source side injection (SSI) flash nonvolatile memory (NVM) devices is evaluated in terms of endurance and disturb effects related to stress induced leakage current (SILC) and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room-T, program/erase (P/E) cycling at 150°C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperature on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up influences the threshold voltage, Vt: 1) the T-enhanced trap generation and 2) the T-enhanced emission of trapped charge which influences the disturb field. In the case of the HIMOS-cell-which is discussed here-long-term nonvolatility can still be guaranteed at 150°C. Finally, bake tests at higher temperatures (250-300°C) have been performed in order to evaluate the persistence of the generated damage. It is found that bulk oxide traps are not cured by the bake and, therefore, no long-term relief of SILC-related disturb effects is expected at 150°C View full abstract»

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  • GaInP/AlGaAs/GaInP double heterojunction bipolar transistors with zero conduction band spike at the collector

    Page(s): 2417 - 2421
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    Al0.11Ga0.89As was used in the base, next to the GaInP collector of a DHBT, to eliminate the conduction band spike. The DHBT's demonstrated high breakdown voltages, BVCEO and BV CBO of 44.5 V and 54.5 V (gain≈20), respectively, for a 1-μm-thick collector doped to 2×1016 cm-3 with no voltage dependence of the current gain. Magneto-transport measurements were made on the AlGaAs bases and indicated limitations on the maximum practical base doping due to the inferior minority electron mobility and lifetime when compared with equivalently doped GaAs. Grading in the base from Al0.11Ga0.89As at the collector to Al0.21Ga0.79As at the emitter introduced a quasielectric field in the base, reduced the base transit time by a factor of ~2.5, and improved the gain over ungraded devices with the same average Al concentration View full abstract»

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  • Tunneling through ultrathin GaAs n++-p++-n ++ barrier grown by molecular layer epitaxy

    Page(s): 2551 - 2554
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    The I-V characteristics of ultrathin GaAs n++-p++ -n++ barrier structures with a 45 Å thick p++ layer grown by molecular layer epitaxy (MLE) have been measured at room temperature and 77 K. The tunneling probability for this structure has been calculated as a function of effective tunneling width. It was found that good agreement between experiment and calculation is obtained when the effective tunneling width is assumed to be 75 Å, which is much smaller than the depletion width about 190 Å measured by C-V method. This fact indicates that the depletion width approximation cannot be used to measure the exact tunneling width for ultrathin barrier devices View full abstract»

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  • An analysis of the kink phenomena in InAlAs/InGaAs HEMT's using two-dimensional device simulation

    Page(s): 2390 - 2399
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    Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology