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Electron Device Letters, IEEE

Issue 12 • Date Dec. 1998

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Displaying Results 1 - 20 of 20
  • Effects of die location on hot-carrier response of plasma-etched NMOS devices

    Page(s): 455 - 457
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    Plasma-process-induced charging voltage for a device may be positive (gate is positive with respect to the substrate) or negative depending on the location of the device on the wafer. The negative charging damage increases the number of trapped holes closer to Si-SiO/sub 2/ interface while the positive charging damage does not. This number of trapped holes also depends on the antenna ratio. The trapped holes closer to the Si-SiO/sub 2/ interface gets compensated by hot electrons injected during hot-carrier stressing. Thus, the type of charging voltage and the antenna size determines the hot-carrier response of a device. In addition, the differences in hot-carrier response for devices with varying antenna ratio are shown to be varying linearly with the differences in prestress subthreshold characteristics. This finding has the potential to reduce the hot-carrier stressing time or determine the most vulnerable devices without actually carrying out the experiments. View full abstract»

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  • Improved stability of short-channel hydrogenated N-channel polycrystalline silicon thin-film transistors with very thin ECR N2O-plasma gate oxide

    Page(s): 458 - 460
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (118 KB)  

    Stability has been investigated for short-channel hydrogenated n-channel polycrystalline thin-film transistors (poly-Si TFTs) with very thin (12 nm) electron cyclotron resonance (ECR) N2O-plasma gate oxide. The TFTs show negligible changes in the electrical characteristics after hot-carrier stresses, which is due to the highly reliable interface and gate oxide. The hydrogenated TFTs with 3-μm gate length TFTs exhibit very small degradation (/spl Delta/V/sub th/<15 mV) under hot-carrier stresses and Fowler-Nordheim (F-N) stress (/spl Delta/V/sub th/=/sub 81/ mV, /spl Delta/Gm/Gm=2.2%, /spl Delta/S/S=4.7%). View full abstract»

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  • Method of creating local semi-insulating regions on silicon wafers for device isolation and realization of high-Q inductors

    Page(s): 461 - 462
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB)  

    Penetrating proton beams from a compact ion cyclotron (diameter: 1.5 m, height: 2 m) were employed to create local semi-insulating regions within silicon substrates to facilitate device isolation in mixed-mode (analog-digital) integrated circuits (IC's) and realization of RF IC's with high-Q inductors. Experiments revealed that resistivity values of I M/spl Omega/-cm could be reached by practical proton fluences on silicon wafers of original resistivity of more than about 1 /spl Omega/-cm. Significant improvement was evidenced on Q values of irradiated inductors. Effect of reduced inductor metal conductivity from bombardment was over-shadowed by the more enhanced Q behavior, if the proton fluence is sufficiently large. View full abstract»

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  • Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

    Page(s): 463 - 465
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    The hot carrier degradation of short channel NMOSFETs (L/sub EFF/=0.07-0.10 μm) stressed at 2.0 V/spl les/V/sub DS//spl les/2.9 V and a wide V/sub GS/ range is shown NOT to obey the classic hot carrier "lucky electron model". In the low and mid V/sub GS/ range, the degradation behavior is better described by an effective electron temperatures model proposed here, which takes e-e scattering effects into account. In the high V/sub GS/ regime, a further lifetime reduction can be qualitatively explained within this model by the increase in electron concentration at the Si-SiO2 interface near the drain region. View full abstract»

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  • GaAs metal insulator field effect transistors with excellent intrinsic transconductance and stable drain currents using (NH/sub 4/)/sub 2/Sx chemical treatment

    Page(s): 466 - 468
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    Metal insulator semiconductor field effect transistors (MISFETs) and MIS capacitors are fabricated using Al metal-gate and PECVD silicon nitride (Si/sub 3/N/sub 4/) gate-insulator on commercial GaAs epitaxial wafers after treating the channel regions with (NH/sub 4/)/sub 2/S/sub x/. It is shown that the post metallization annealing (PMA) of these devices improves the transconductance and reduces the interface state density (D/sub it/) considerably. This is attributed to the additional passivation effect of hydrogen diffusing to the interface from the Si/sub 3/N/sub 4/ during the PMA. An intrinsic transconductance of 30.7 mS/mm which is 75% of the theoretical maximum limit of 40.5 mS/mm has been achieved using silicon nitride gate insulator thickness of 1100 /spl Aring/. Stability of the drain currents in these devices is demonstrated to be excellent. View full abstract»

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  • A short-term high-current-density reliability investigation of AlGaAs/GaAs heterojunction bipolar transistors

    Page(s): 469 - 471
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    In high current and power density applications of AlGaAs/GaAs heterojunction bipolar transistors (HBT's), reliability is a critical issue. Therefore, in this letter we show results of a fundamental investigation on the temperature and current dependence of the fast initial rise of the dc-current gain (burn-in), which takes place during stress at current densities beyond those of today's applications. We find that the burn-in occurs at lower device junction temperatures (135/spl deg/C) than previously reported in literature, and that it depends linearly on the current density. An activation energy of 0.4 eV is extracted for the burn-in effect. View full abstract»

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  • Characteristics of InAlAs/InGaAs high electron mobility transistors under 1.3-μm laser illumination

    Page(s): 472 - 474
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    The current-voltage (I-V) characteristics of InAlAs/InGaAs high electron mobility transistors (HEMTs) under illumination are investigated. The change of the drain current caused by the illumination can be explained by using the photovoltaic effect so that the excess holes photo-generated in the InGaAs channel layer accumulate at the source-electrode region and cause an effective decrease in the potential barrier for electrons between the source and the channel. The basic equations describing this phenomenon are derived on the basis of the experimental results. In addition, our experimental results are shown to support the barrier-induced hole pile-up model in which holes generated by the impact ionization accumulate in the InAlAs barrier on the source side and cause the kink effect In InAlAs/InGaAs HEMTs. View full abstract»

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  • Flicker noise in GaN/Al/sub 0.15/Ga/sub 0.85/N doped channel heterostructure field effect transistors

    Page(s): 475 - 477
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    We have investigated noise characteristics of novel GaN/Al/sub 0.15/Ga/sub 0.85/N doped channel heterostructure field effect transistors designed for high-power density applications. The measurements were carried out for various gate bias voltages V/sub GS/ and with the drain voltage V/sub DS/ varying from the linear to the saturation regions of operation V/sub DS/>5 V. Our results show that flicker, e.g., 1/f noise, is the dominant limiting noise of these devices; and the Hooge parameter is of the order of 10/sup -5/-10/sup -4/. The gate voltage dependence of 1/f noise was observed in the linear region for all examined V/sub GS/ and in the saturation region for V/sub GS/>0. These results indicating low values of the Hooge parameter are important for microwave applications. View full abstract»

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  • Planar integration of a resonant-tunneling diode with pHEMT using a novel proton implantation technique

    Page(s): 478 - 480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (76 KB)  

    A novel technique of integrating resonant-tunneling diodes (RTDs) with pseudomorphic high-electron-mobility transistors (pHEMTs) is demonstrated. A proton was implanted through the pHEMT layers to convert the RTD structure underneath to a high-resistivity buffer without degrading the performance of the pHEMT. The cutoff frequency is 16 GHz for a 1.5-μm-gate-length pHEMT on such an implanted buffer. Substituting the conventional deep mesa etch with ion implantation maintains a highly planar surface. Such a monolithically integrated RTD/pHEMT oscillator is described. View full abstract»

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  • Improved uniformity of contact resistance in GaAs MESFET using Pd/Ge/Ti/Au ohmic contacts

    Page(s): 481 - 483
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (326 KB)  

    Improved contact resistance uniformity, with a low resistance on high-low doped GaAs MESFET, was demonstrated using a Pd/Ge/Ti/Au ohmic contact. The lowest contact resistivity obtained was 2.8/spl times/10/sup -6/ /spl Omega/-cm/sup 2/. The average value and standard deviation (/spl Delta/Rc) of the contact resistance (Rc) were 0.73 and 0.07 /spl Omega/-mm, respectively, which were more uniform than those for AuGe/Ni contacts with an average Rc of 0.77 /spl Omega/-mm and /spl Delta/Rc of 0.16 /spl Omega/-mm. The improved uniformity was attributed to the uniform penetration of the ohmic junction into the buried high-doped channel layer by solid-state reactions, resulting in the improved uniformity of device performance. View full abstract»

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  • Self-compensation of short-channel effects in sub-0.1-μm InAlAs/InGaAs MODFETs by electrochemical etching

    Page(s): 484 - 486
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (58 KB)  

    We show that by making full use of the features of electrochemical etching in InAlAs/InGaAs heterostructures, deep gate grooves with small side etching can be fabricated. The most important advantage of this technology is that the vertical etching in the small gate openings will be remarkably enhanced by a self-organized process. Therefore the electrochemical etching provides a what we call "self-compensation" of the short channel effects. The effectiveness of this technology is evidenced by the excellent performance combined with the alleviation of the threshold-voltage shift and suppression of transconductance degradation in MODFET's with gate lengths below 0.1 μm. View full abstract»

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  • High-voltage accumulation-layer UMOSFET's in 4H-SiC

    Page(s): 487 - 489
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    A novel silicon carbide UMOSFET structure is reported. This device incorporates two new features: a self-aligned p-type implantation in the bottom of the trench that reduces the electric field in the trench oxide, and an n-type epilayer under the p-base to promote lateral current spreading into the drift region. This UMOS structure is capable of supporting the full blocking voltage of the pn junction while keeping the electric field in the gate oxide below 4 MV/cm. An accumulation channel is formed on the sidewalls of the trench by epigrowth, and the gate oxide is produced by a polysilicon oxidation process, resulting in a uniform oxide thickness over both the sidewalls and bottom of the trench. The fabricated 4H-SiC devices have a blocking voltage of 1400 V (10 μm drift region), a specific on-resistance of 15.7 m/spl Omega/-cm2 at room temperature, and a gate oxide field of 3 MV/cm. View full abstract»

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  • A new gradual hole injection dual-gate LIGBT

    Page(s): 490 - 492
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (41 KB)  

    A new shorted-anode lateral insulated gate bipolar transistor (SA-LIGBT), entitled gradual hole injection dual gate LIGBT (GHI-LIGBT), is proposed and fabricated. The new device employs a dual gate and p/sup +/ injector in order to initiate the hole injection gradually from the anode electrode into the drift region so that the negative differential resistance (NDR) regime may be eliminated. The experimental results show that the NDR regime, which may cause undesirable device characteristics, is completely eliminated in the GHI-LIGBT, and the forward voltage drop is reduced by 1 V at the current density of 200 A/cm/sup 2/ in comparison with the conventional SA-LIGBT. View full abstract»

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  • CB-BRT: a new base resistance-controlled thyristor employing a self-aligned corrugated p-base

    Page(s): 493 - 495
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (60 KB)  

    We propose and fabricate a new base resistance-controlled thyristor (BKT) employing a self-aligned corrugated p-base. The new device, entitled CB-BRT, suppresses the snap-back effectively and increases the maximum controllable current. Experimental results show that the snap-back of the CB-BRT is reduced significantly when compared with that of the conventional BRT. Also, the maximum controllable current of the CB-BRT increases as compared with the conventional BRT. View full abstract»

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  • Resonant mechanical magnetic sensor in standard CMOS

    Page(s): 496 - 498
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (126 KB)  

    A novel micromechanical magnetic sensor has been built and tested. The field is detected by measuring the vibration amplitude of a mechanical Lorentz force oscillator. This device is made from a standard 2-μm CMOS fabrication process with a post-processing etch step to undercut and release the sensor. When operated at the resonant frequency of the mechanical system, a sensitivity of 20 μV/G was measured. View full abstract»

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  • Transient measurements of SOI body contact effectiveness

    Page(s): 499 - 501
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (64 KB)  

    A technique for characterizing the effectiveness of SOI MOSFET body contacts under transient conditions, by measuring the transient lateral bipolar current in a SOI pass gate, is demonstrated. Using this technique, the minimum rise or fall edge rate required to guarantee that the body potential over the device width follows the contact potential is defined. While this technique is applied specifically to a Schottky body tie, it can be generalized to other technologies and other body ties. View full abstract»

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  • High-performance polycrystalline SiGe thin-film transistors using Al2O3 gate insulators

    Page(s): 502 - 504
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (66 KB)  

    The use of aluminum oxide as the gate insulator for low temperature (600/spl deg/C) polycrystalline SiGe thin-film transistors (TFTs) has been studied. The aluminum oxide was sputtered from a pure aluminum target using a reactive N/sub 2/O plasma. The composition of the deposited aluminum oxide was found to be almost stoichiometric (i.e., Al/sub 2/O/sub 3/), with a very small fraction of nitrogen incorporation. Even without any hydrogen passivation, good TFT performance was measured an devices with 50-nm-thick Al/sub 2/O/sub 3/ gate dielectric layers. Typically, a field effect mobility of 47 cm/sup 2//Vs, a threshold voltage of 3 V, a subthreshold slope of 0.44 V/decade, and an on/off ratio above 3/spl times/10/sup 5/ at a drain voltage of 0.1 V can be obtained. These results indicate that the direct interface between the Al/sub 2/O/sub 3/ and the SiGe channel layer is sufficiently passivated to make Al/sub 2/O/sub 3/ a better alternative to grown or deposited SiO/sub 2/ for SiGe field effect devices. View full abstract»

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  • Improving low-temperature APCVD SiO2 passivation by rapid thermal annealing for Si devices

    Page(s): 505 - 507
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    The quality of low-temperature (/spl ap/400/spl deg/C) atmospheric pressure chemical vapor deposited (APCVD) silicon dioxide (SiO/sub 2/) films has been improved by a short time rapid thermal annealing (RTA) step. The RTA step followed by a low temperature (400/spl deg/C) forming gas anneal (FGA) results in a well-passivated Si-SiO/sub 2/ interface, comparable to thermally grown conventional oxides. Efficient and stable surface passivation is obtained by this technique on virgin silicon as well as on photovoltaic devices with diffused (n/sup +/p) emitter surface while maintaining a very low thermal budget. Device parameters are improved by this APCVD/RTA/FGA passivation process. View full abstract»

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  • Influence of line dimensions on the resistance of Cu interconnections

    Page(s): 508 - 510
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (68 KB)  

    As dimensions reach the deep-submicrometer level on the order of the mean-free path of electrons, increases in the resistivity of a metal corresponding to reductions of wire dimensions is a concern. To understand the resistance dependence on the dimensions, resistance of Cu versus interconnection size was analyzed. The experimental values were in good agreement with Fuchs' size-effect theory. The resistance of Cu increased nonlinearly as line width decreased. This enhancement was attributed to the increased surface and grain boundary scattering. Almost 50% of the electrons elastically scatter during transport in wires with widths below 0.5 μm. It will he important in the future to develop interconnections with smooth surfaces on all sides to maximize elastic scattering of electrons. View full abstract»

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  • Comprehensive analysis of reverse short-channel effect in silicon MOSFETs from low-temperature operation

    Page(s): 511 - 513
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    The reverse short channel effect (RSCE) is a major issue for deep-submicron CMOS technologies. In this paper, the RSCE is studied over a wide range of temperature (from 300 K down to 30 K). It is shown that the temperature lowering results in a significant reduction of the RSCE. Moreover, we show using these low temperature experiments that the RSCE arises from an excess doping concentration near the source and drain as supported from both analytical modeling and two-dimensional (2-D) numerical simulation. View full abstract»

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