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Computers and Digital Techniques, IEE Proceedings E

Issue 1 • Date Jan 1990

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Displaying Results 1 - 11 of 11
  • Co-operative computing and control

    Publication Year: 1990 , Page(s): 1 - 16
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1104 KB)  

    The pace of innovation in the information technologies continues unabated, and massive investment in the digital infrastructure required for distributed information systems is proceeding steadily. The paper summarises some of the basic technology trends of the past five years and describes some of the consequent systems trends, including workstation networks, open system standards, digital communications and computer supported co-operative work. A key characteristic of most of these developments is the need for systems that support co-operation between people, between people and machines, between machines, and between organisations. Some examples of these are discussed including X400 electronic mail, CCITT SS7 separate channel signalling and electronic conferencing. Some of the newer disciplines required to support an engineering approach to building very large distributed information systems are then described, including protocol engineering, distributed systems architecture, object-oriented design and system control and management. The paper concludes by reviewing some of the issues these technologies raise for the engineering professional and the role of the IEE in the 1990s. View full abstract»

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  • Four-slot fully asynchronous communication mechanism

    Publication Year: 1990 , Page(s): 17 - 30
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1328 KB)  

    The paper is concerned with communication mechanisms in which a record in shared memory is maintained by a writer to provide a coherent and up-to-date data reference which may be accessed at any time by a reader. The dynamic properties of several possible designs are briefly discussed before concentrating on a fully asynchronous form called a four-slot mechanism. This takes its name from the four-element array through which data is routed. Coherence is maintained by means of an orthogonal avoidance strategy without recourse to conventional synchronisation techniques such as semaphores, rendezvous, monitors or critical sections. Various implementation options are considered including software and hardware designs. It is seen that the fully asynchronous mechanism completes the range of basic communications options available to digital system designers. View full abstract»

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  • Universal shift matrix

    Publication Year: 1990 , Page(s): 57 - 64
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    Serial shifting techniques are slow whereas a totally parallel approach, though fast, is impractical for implementational reasons. A novel intermediate approach is presented whereby circular shifting is performed over two or three levels depending on the factorisation of the shift length n. The use of read-only memories to control its operation and to provide arithmetic and logical shifting produces a hardware structure which can be automatically generated by software for use in cell-based integrated circuit design. This implementation is compared for CMOS and bipolar differential mode logic. View full abstract»

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  • Hierarchical design of delay-insensitive systems

    Publication Year: 1990 , Page(s): 41 - 56
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1116 KB)  

    A set of building blocks is presented for the hierarchical design of delay-insensitive systems. It consists of delay-insensitive (DI) building blocks and hybrid (non-DI) building blocks. An extended signal transition graph (STG) model is used for circuit specification and analysis. It permits the clear specification of delay-insensitive circuits, distinguishing between environment/module behaviour and DI/non-DI components. A hierarchical composition procedure is described for the composition of deterministic STG specifications. As an example, a circuit for distributed mutual exclusion is designed and implemented. View full abstract»

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  • Transformation of timed Petri nets for response time estimation

    Publication Year: 1990 , Page(s): 74 - 80
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (588 KB)  

    Proposes a transformation method for the simplification of timed Petri nets to estimate the response time. A complicated time Petri net which is live and safe is transformed into a simpler one with a smaller state space by hierarchically replacing a convertible subnet with the corresponding decision net. It is shown that the information for the response time analysis is not lost but is kept during the transformation. An illustrative example is given. View full abstract»

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  • Efficient characterisation of cellular automata

    Publication Year: 1990 , Page(s): 81 - 87
    Cited by:  Papers (9)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (452 KB)  

    The paper characterises cellular automata (CA) with the help of matrix algebra. It has been shown how k-neighborhood additive CA rules (uniform, complemented and hybrid) can be represented with the help of a characteristic matrix representing the CA. Further, the paper discusses how the global group properties of the automata depend on the hybridisation of rules, the length of the automata, the starting state, etc. View full abstract»

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  • Implementation of 32-bit RISC processor incorporating hardware concurrent error detection and correction

    Publication Year: 1990 , Page(s): 88 - 102
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1064 KB)  

    The need for reliable integrated circuits is becoming of paramount importance as they are increasingly used in a range of safety critical applications or domestic products. In the past reliability has been achieved at the IC level by comprehensive testing of the device after manufacture. The use of scan design and BILBO techniques have assisted designers in achieving the necessary high test coverages with little effort. However these methods only address the problem of testing for permanent faults after fabrication or periodically during the lifetime of a system. These 'classical' techniques do not tackle the more serious problem of intermittent faults, which will come to dominate VLSI circuits as device geometries decrease. To deal with intermittent faults and maintain reliable operation concurrent test methods need to be used. The paper presents one possible method of detecting and correcting single intermittent faults that occur during normal operation and also assist the designer in post fabrication testing. The chosen technique uses information redundancy in the form of a SEC/DED Hamming code and is illustrated by the design of a 32-bit CMOS RISC processor. The processor is capable of detecting and correcting errors arising from faults as they occur without the need to halt normal operations or recourse to any specialised software. A detailed appraisal of the costs involved in using this technique is given in terms of the extra silicon area needed and the reduction in throughout of the processor. View full abstract»

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  • Traffic routing algorithm for serial superchip system customisation

    Publication Year: 1990 , Page(s): 65 - 73
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    A traffic routing algorithm is presented for system customisation of the serial superchip architecture. In modern signal processing and scientific computation, system reconfigurability is highly desired to achieve dynamic reconfiguration during system operation and static reconfiguration. For example, for defect/fault tolerance before system operation. The superchip architecture is aimed at achieving both dynamic and static reconfigurability. The algorithm introduced here is intended to help system designers customise a superchip (which may be partially good) at the systems level. The algorithm will optimally search for traffic routes according to the connectivity information extracted from system specification, while avoiding defective elements on the chip. View full abstract»

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  • Linear quadtree algorithms for transputer array

    Publication Year: 1990 , Page(s): 114 - 128
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (1080 KB)  

    The quadtree is a hierarchical data model based upon a regular recursive decomposition of space, which has been found useful in such areas as image processing, computer graphics, cartography and spatial information systems. The linear quadtree is a pointerless representation of the quadtree. In the paper, a number of linear quadtree algorithms are presented for a transputer array. These form a largely complementary set to those developed by Bhaskar et al. (1988) for a similar multiprocessor architecture. Emphasis is placed on algorithms which require the neighbours of quadtree leaves to be accessed. These include perimeter computation, connected component labelling and image dilation. A quadtree generation algorithm is also described. Timing estimates have been carried out using a transputer development system. A price to be paid for the speed increases achieved is an increase in the complexity of the multiprocessor algorithms. View full abstract»

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  • Reed-Muller canonical forms with mixed polarity and their manipulations

    Publication Year: 1990 , Page(s): 103 - 113
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    The set of 3n consistent mixed-polarity Reed-Muller canonical forms of an n-variable switching function is described and the means whereby each form may be derived by a transform on the zero-polarity form is investigated. The computational cost of deducing the optimum polarity expansion is evaluated for various strategies. A ternary map-based method is introduced which enables this search and other operations to be performed in a compact and efficient manner. View full abstract»

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  • Survey of square rooting algorithms

    Publication Year: 1990 , Page(s): 31 - 40
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (912 KB)  

    The paper reviews the algorithms for the computation of square roots for binary machines. After an initial classification, the algorithms are analysed in detail by considering their specific peculiarities and properties. Finally, some comments are made regarding their ideal and effective implementation in hardware, software or microcode. View full abstract»

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