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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 10 • Date Oct 1998

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Displaying Results 1 - 13 of 13
  • Faster maximum and minimum mean cycle algorithms for system-performance analysis

    Page(s): 889 - 899
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    Maximum and minimum mean cycle problems are important problems with many applications in performance analysis of synchronous and asynchronous digital systems including rate analysis of embedded systems, in discrete-event systems, and in graph theory. Karp's algorithm is one of the fastest and most common algorithms for these problems. We present this paper mainly in the context of the maximum mean cycle problem. We show that Karp's algorithm processes more nodes and arcs than needed to find the maximum cycle mean of a digraph. This observation motivated us to propose a new graph-unfolding scheme that remedies this deficiency and leads to two faster algorithms with different characteristics. Theoretical analysis tells us that our algorithms always run faster than Karp's algorithm and that they are among the fastest to date. Experiments on small benchmark graphs confirm this fact for most of the graphs. These algorithms have been used in building a framework for analysis of timing constraints for embedded systems View full abstract»

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  • Circuit optimization using carry-save-adder cells

    Page(s): 974 - 984
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    Carry-save-adder (CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer-level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation duplication and operation split, which are the main driving techniques of our algorithm for achieving an extensive utilization of CSAs. Experimental results from a set of typical arithmetic computations found in industry designs indicate that automating CSA optimization with our algorithm produces designs with up to 53% faster timing and up to 42% smaller area View full abstract»

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  • A graph representation for programmable logic arrays to facilitate testing and logic design

    Page(s): 1030 - 1043
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic ran be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLAs. Thus, this graph model can unify the data structure and operations required in PLA design and test View full abstract»

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  • Behavioral optimization using the manipulation of timing constraints

    Page(s): 936 - 947
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    We introduce a transformation, named rephasing, that manipulates the timing parameters in control-data-flow graphs (CDFG's) during the high-level synthesis of data-path-intensive applications. Timing parameters in such CDFG's include the sample period, the latencies between input-output pairs, the relative times at which corresponding samples become available on different inputs, and the relative times at which the corresponding samples become available at the delay nodes. While some of the timing parameters may be constrained by performance requirements, or by the interface to the external world, others remain free to be chosen during the process of high-level synthesis. Traditionally high-level synthesis systems for data-path-intensive applications either have assumed that all the relative times, called phases, when corresponding samples are available at input and delay nodes are zero (i.e., all input and delay node samples enter at the initial cycle of the schedule) or have automatically assigned values to these phases as part of the data-path allocation/scheduling step in the case of newer schedulers that use techniques like overlapped scheduling to generate complex time shapes. Rephasing, however, manipulates the values of these phases as an algorithm transformation before the scheduling/allocation stage. The advantage of this approach is that phase values can be chosen to transform and optimize the algorithm for explicit metrics such as area, throughput, latency, and power. Moreover, the rephasing transformation can be combined with other transformations such as algebraic transformations. We have developed techniques for using rephasing to optimize a variety of design metrics, and our results show significant improvements in several design metrics. We have also investigated the relationship and interaction of rephasing with other high-level synthesis tasks View full abstract»

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  • Test sequences to achieve high defect coverage for synchronous sequential circuits

    Page(s): 1017 - 1029
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    Test sets that detect each stuck-at fault n>1 times (called n-detection stuck-at test sets) were shown to be effective in achieving high defect coverages. In addition, a pseudofunctional fault model defined before was shown to result in test sets having similar defect coverages. Previous studies of n-detection stuck-at test sets and pseudofunctional test sets were for combinational circuits, In this paper, we study detection stuck-at test sequences and pseudofunctional test sequences for synchronous sequential circuits. Considering stuck-at faults, we propose five definitions of the number of detections achieved by a test sequence. These definitions lead to five different definitions of n-detection stuck at test sequences. We discuss the effects of these definitions on fault-simulation and test-generation procedures and present experimental results for benchmark circuits to evaluate their relative effectiveness. The experimental results indicate the usefulness of the simplest definition in generating test sequences that achieve improved defect coverages. We also describe a pseudofunctional fault model that extends previous definitions. We describe fault-simulation and test-generation methods for this model and give experimental data to evaluate its effectiveness. The results indicate that this model too can be used to generate test sequences with improved defect coverage. Its advantages and disadvantages compared to the n-detection stuck-at model are also considered View full abstract»

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  • COHRA: hardware-software cosynthesis of hierarchical heterogeneous distributed embedded systems

    Page(s): 900 - 919
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (504 KB)  

    Hardware-software cosynthesis of an embedded system architecture entails partitioning of its specification into hardware and software modules such that its real-time and other constraints are met. Embedded systems are generally specified in terms of a set of acyclic task graphs. For medium- to large-scale embedded systems, the task graphs are usually hierarchical in nature. The embedded system architecture, which is the output of the cosynthesis system, may itself be nonhierarchical or hierarchical. Traditional nonhierarchical architectures create communication and processing bottlenecks and are impractical for large embedded systems. Such systems require a large number of processing elements and communication links connected in a hierarchical manner, thus forming a hierarchical distributed architecture, to meet performance and cost objectives. In this paper, we address the problem of hardware-software cosynthesis of hierarchical heterogeneous distributed embedded system architectures from hierarchical or nonhierarchical task graphs. Our cosynthesis algorithm has the following features: 1) it supports periodic task graphs with real-time constraints, 2) it supports pipelining of task graphs, 3) it supports a heterogeneous set of processing elements and communication links, 4) it allows both sequential and concurrent modes of communication and computation, 5) it employs a combination of preemptive and nonpreemptive static scheduling, 6) it employs a new task-clustering technique suitable for hierarchical task graphs, and 7) it uses the concept of association arrays to tackle the problem of multirate tasks encountered in multimedia systems. We show how our cosynthesis algorithm can be easily extended to consider fault tolerance or low-power objectives or both. Although hierarchical architectures have been proposed before, to the best of our knowledge, this is the first time the notion of hierarchical task graphs and hierarchical architectures has been supported in a cosynthesis algorithm View full abstract»

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  • Iterative remapping for logic circuits

    Page(s): 948 - 964
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology library, the network is optimized by finding optimal replacements to clusters of two or more cells at the same time. We leverage a generalized matching algorithm that finds symbolically all possible matching assignments of library cells to a multioutput network specified by a Boolean relation and automatically selects the minimum cost replacement. The remapping technique can be applied to area minimization under delay constraints, power minimization under delay constraints, and unconstrained delay minimization. Our remapping tool is based on a fully symbolic algorithm geared toward flexibility and robustness. The tool has been tested on a large set of benchmark circuits. The quality of the results proves the practical relevance of the technique. We obtain sizable improvements in (i) speed (6% in average, up to 20.7%), (ii) area under speed constraints (13.7% in average, up to 29.5%), and (iii) power under speed constraints (22.3% in average, up to 38.1%) View full abstract»

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  • Guarded evaluation: pushing power management to logic synthesis/design

    Page(s): 1051 - 1060
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    The need to reduce the power consumption of the next generation of digital systems is clearly recognized at all levels of system design. At the system level, power management is a very powerful technique and delivers large and unambiguous savings. The ideas behind power management can be extended to the logic level. This would involve determining which parts of a circuit are computing results that will be used and which are not. The parts that are not needed are then “shut off”. This paper describes an approach termed guarded evaluation, which is an implementation of this idea. A theoretical framework and the algorithms that form the basis of the approach are presented. The underlying idea is to automatically determine the parts of the circuit that can be disabled on a per-clock-cycle basis. This saves the power used in all the useless transitions in those parts of the circuit. Initial experiments indicate substantial power savings and the strong potential of this approach for a large number of benchmark circuits. While this paper presents the development of these ideas at the logic level of design, the same ideas have direct application at the register-transfer level of design also View full abstract»

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  • Characterization and parameterized generation of synthetic combinational benchmark circuits

    Page(s): 985 - 996
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    The development of new field-programmed, mask-programmed, and laser-programmed gate-array architectures is hampered by the lack of realistic test circuits that exercise both the architectures and their automatic placement and routing algorithms. In this paper, we present a method and a tool for generating parameterized and realistic synthetic circuits. To obtain the realism, we propose a set of graph-theoretic characteristics that describe a physical netlist, and have built a tool that can measure these characteristics on existing circuits. The generation tool uses the characteristics as constraints in the synthetic circuit generation. To validate the quality of the generated netlists, parameters that are not specified in the generation are compared with those of real circuits and with those of more “random” graphs View full abstract»

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  • Design of built-in test generator circuits using width compression

    Page(s): 1044 - 1051
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    We present a method for designing test generator circuits (TCCs) that incorporate a precomputed test set TD in the patterns they produce. Our method uses width compression based on the property of d-compatibles as well as compatibles and inverse compatibles and does not require access to a gate-level model of the circuit under test. The TGC consists of a counter, which generates a set of encoded test patterns TE and a decompression circuit, which consists of simple binary decoders that generate a final sequence containing TD . We show that partially specified test sets, i.e., those that contain a large number of don't-cares, lead to more efficient TGCs. These TGCs are applicable to embedded core circuits whose detailed designs are not available. We demonstrate the effectiveness of our approach by presenting experimental results on width compression for the ISCAS'85 benchmark circuits and the full-scan versions of the ISCAS'89 benchmark circuits View full abstract»

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  • Full-wave analysis of high-speed interconnects using complex frequency hopping

    Page(s): 997 - 1016
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (580 KB)  

    Accurate simulation of large interconnect networks has become a necessity to address signal-integrity issues in current high-speed very-large-scale-integration designs. To accurately characterize a dispersive system of interconnects at higher frequencies, a full-wave analysis is required. However, conventional circuit simulation of interconnects with full-wave models is extremely CPU expensive. Recently published moment-matching techniques provide a generalized approach to lumped/distributed circuit response approximations. However, these techniques are based on quasi-transverse electromagnetic mode (TEM) assumption and have no mechanism to handle full-wave models. In this paper, we present a new method to extend model-reduction techniques for simulation of full-wave models. The following three new results are presented in this paper: 1) a generalized method to combine modal results from a full-wave analysis into circuit simulators; 2) a new algorithm for moment generation involving full-wave models; 3) deviations associated with quasi-TEM approximations compared to full-wave models at higher frequencies. The proposed algorithm yields a speed up of 1 to 2 orders of magnitude for a comparable accuracy with conventional techniques. In addition, the proposed method can be used for a mixed simulation involving distributed models with frequency dependent/independent RLCG parameters, full-wave interconnect models and measured subnetworks along with nonlinear terminations View full abstract»

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  • MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems

    Page(s): 920 - 935
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    In this paper, we present a hardware-software cosynthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multirate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single cosynthesis run to produce multiple designs that trade off different architectural features. Experimental results indicate that MOGAC has advantages over previous work in terms of solution quality and running time View full abstract»

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  • Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions

    Page(s): 965 - 973
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    Ordered Kronecker functional decision diagrams (OKFDD's) are a data structure for efficient representation and manipulation of Boolean functions. OKFDD's are a generalization of ordered binary decision diagrams (OBDD)s) and ordered functional decision diagrams and thus combine the advantages of both. In this paper, basic properties of OKFDD's and their efficient representation and manipulation are given. Starting with elementary manipulation algorithms, we present methods for the construction of small OKFDD's. Our approach is based on dynamic variable ordering and decomposition-type choice. For changing the decomposition type, we use an efficient reordering-based method. We briefly discuss the implementation of PUMA, an OKFDD package, which was used in all our experiments. These experiments demonstrate the quality of our methods in comparison to sifting and interleaving for OBDD's View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

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Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu