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Computers and Digital Techniques, IEE Proceedings -

Issue 5 • Date Sep 1998

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Displaying Results 1 - 7 of 7
  • Algebraic properties of multiple-valued modulo systems and their applications to current-mode CMOS circuits

    Publication Year: 1998 , Page(s): 364 - 368
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (420 KB)  

    The paper presents the concepts of pseudoprime and modulo correlativity and establishes the relationships among completeness of modulo operations, uniqueness of solution of equations, invertibility of a square matrix, and correlativity of vectors in multiple-valued modulo system. It is shown that current-mode CMOS circuits are easy to design and economical using bounded operations View full abstract»

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  • Cylindrical architectures for 1-D recursive digital filters: A state space approach

    Publication Year: 1998 , Page(s): 327 - 332
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    The paper considers the array processors' implementation of finite impulse response digital filters that require recursive computations. The state space representation is used to obtain efficient implementation via dynamically switchable systolic arrays (cylindrical type) of 1-D direct realisation. This direct description leads to a reduction in the computation speed and the throughput rate. Two solutions are proposed to improve the array performance: the use of sparse matrices representing the filters is shown to considerably reduce the hardware complexity and the effect of feedback delays, consequently improving the throughput rate. The use of fast form algorithms of Porter-Aravena is also considered as an approach to design IIR filters via much faster cylindrical architectures View full abstract»

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  • Generalised inverses in public key cryptosystem design

    Publication Year: 1998 , Page(s): 321 - 326
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The theory of generalised inverses of matrices over finite fields is highlighted potential tool in cryptographic research, by proposing a public key cryptosystem. Properties of the public key cryptosystem are analysed and compared with those of a previous public key cryptosystem. The idea is similar to the previous cryptosystem in terms of the usage of an error correction process. However, by using the techniques of generalised matrices, the Hamming weight of the error pattern in the cryptosystem is far larger than the error correction capability of the employed error-correcting code. This is the main reason that the key size is smaller than that of the previous public key cryptosystem with the same level of security. It is also anticipated that the theory of generalised inverses can be used for a wide variety of cryptographic applications View full abstract»

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  • Logical manipulations and design of tributary networks in the arithmetic spectral domain

    Publication Year: 1998 , Page(s): 347 - 356
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    Formulae to represent composite arithmetic spectra of switching functions for basic logic connectives of such functions are shown. In contrast to the Walsh spectral domain, no complex dyadic convolution is involved in the calculation of composite arithmetic spectra, and the reintroduction of the transformation matrix has been avoided in the final formulae. Other important operations used in classification and optimisation of standard and tributary logical network have also been analysed in the arithmetic spectral domain. These operations include spectral decomposition, input and output negations, permutations of input variables, substitution of an input variable by a logical operation with some input variables or by the output of the function and the variable itself. Based on the introduced formulae, a new method to design tributary networks through operations on arithmetic spectra is shown View full abstract»

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  • Memory alignment issues in real-time systems

    Publication Year: 1998 , Page(s): 341 - 346
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (484 KB)  

    Real-time systems are proliferating, with applications in aircraft, spacecraft, chemical and power plants, and potentially in automobile-control systems. An important issue in such systems is aligning the memories of the processors after a transient failure. The authors show how the need to do this impacts system reliability, and should influence the amount of redundancy used as well as the task assignment View full abstract»

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  • Stack operations folding in Java processors

    Publication Year: 1998 , Page(s): 333 - 340
    Cited by:  Papers (4)  |  Patents (15)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (832 KB)  

    Traditionally, the performance of a stack machine has been limited by the true data dependency. A performance enhancement mechanism, stack operations folding, was used in Sun Microelectronics' picoJava-I design, and it can fold up to 60% of all stack operations. The authors use the Java bytecode language as the target machine language, and study Java instruction folding on a proposed folding model, the POC model, which is used to illustrate the theoretical folding operations, Various practical folding strategies based on the POC model are introduced and evaluated. Statistical data show that the 4-foldable strategy eliminates 84% of all stack operations, and the 2-, 3-, and 4-foldable strategies result in overall program speedups of 1.22, 1.32 and 1.34, respectively, as compared to a stack machine without folding. Furthermore, the 4-foldable strategy is the most practical and cost effective of a Java stack machine design with a decoder width of 8 bytes. Circuit simulation results show that a 100 MHz 4-foldable folding mechanism can be realized with 0.6 μm CMOS standard cells, or 240 MHz with 0.25 μm CMOS technology View full abstract»

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  • Method for minimising the switching activity of two-level logic circuits

    Publication Year: 1998 , Page(s): 357 - 363
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    A new approach for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by inserting additional input signals in specific gates. Based on the statistical properties (i.e. static and transition probabilities) of the primary inputs, a new concept for grouping the input variables with similar features is presented. An efficient synthesis algorithm for generating the set of all classes of the variables, and solving the minimum covering problem for each class is developed. A comparison of the results produced by the proposed method, and those from ESPRESSO, shows that substantial power reduction can be achieved View full abstract»

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