Issue 11 • Date Nov. 1998
Filter Results
Displaying Results 1 - 25 of 32
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Introduction To The Digital Section
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PDF (15 KB)
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Introduction to the memory section
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PDF (16 KB)
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Introduction To The Signal Processing Section
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PDF (17 KB)
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An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)
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PDF (104 KB)
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Fully parallel 30-MHz, 2.5-Mb CAM
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PDF (164 KB)
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A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system
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PDF (244 KB)
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An energy/security scalable encryption processor using an embedded variable voltage DC/DC converter
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PDF (284 KB)
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A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme
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PDF (212 KB)
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A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications
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PDF (196 KB)
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A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator
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PDF (144 KB)
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A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM
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PDF (200 KB)
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A process-independent, 800-MB/s, DRAM byte-wide interface featuring command interleaving and concurrent memory operation
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PDF (344 KB)
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0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard
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PDF (272 KB)
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A 480-MHz RISC microprocessor in a 0.12-μm Leff CMOS technology with copper interconnects
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PDF (224 KB)
Aims & Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.
Meet Our Editors
Editor-in-Chief
Un-Ku Moon
Oregon State University, EECS


