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Electron Devices, IEEE Transactions on

Issue 10 • Date Oct 1998

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Displaying Results 1 - 25 of 25
  • Effect of diamond-like carbon coating on the emission characteristics of molybdenum field emitter arrays

    Page(s): 2232 - 2237
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    We have studied the electron emission characteristics of Mo field emitter arrays (FEAs) using a diamond-like carbon (DLC) film deposited by a layer-by-layer technique using plasma enhanced chemical vapor deposition. The turn-on voltage was lowered from 55 to 30 V by a 20 nm thick hydrogen-free DLC coating and maximum emission current was increased from 166 to 831 μA. Also the gate voltage required to get the anode current of 0.1 (μA/emitter) decreases from 77 to 48 V. Furthermore, the emission current from DLC coated Mo FEAs is more stable than that of noncoated Mo FEAs View full abstract»

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  • Electrothermal simulations in punchthrough and nonpunchthrough IGBT's

    Page(s): 2222 - 2231
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    The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBT's) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBT's show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs View full abstract»

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  • An analytical grain-barrier height model and its characterization for intrinsic poly-Si thin-film transistor

    Page(s): 2245 - 2247
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    An analytical model for the grain-barrier height of the intrinsic poly-Si thin-film transistors (TFTs) is developed, in which the grain-barrier height for the applied gate voltage smaller than the threshold voltage is obtained by solving the charge neutrality equation and the grain-barrier height for the applied gate voltage larger than the threshold voltage is obtained by using the quasi-two-dimensional (2-D) method. Good agreements between experimental and simulation results are obtained for a wide gate voltage range View full abstract»

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  • A physical simulation model for field emission triode

    Page(s): 2238 - 2244
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A simple but accurate physical model, which can be incorporated into circuit simulation programs such as SPICE for the field emission triode (FET), is developed. The model is based on the Fowler-Nordheim (F-N) current density-electric field (J-E) relationship. An electric field form is adopted to calculate the current density distribution along the surface of the sphere-shape tip. The cathode current is obtained by integration of the current density over the emission surface. The gate current is derived by the same integration, but over part of the emission area. A procedure to extract the values for the parameters of the model is also given. The model and the procedure has been applied to experimental devices to demonstrate its accuracy View full abstract»

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  • A compact pre- and post-stress I-V model for submicrometer buried-channel pMOSFETs

    Page(s): 2167 - 2178
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    In this paper, we report a new complete and analytical drain current model for pre- and post-stress submicrometer buried-channel (BC) MOSFETs operated in the forward- and reverse-biased modes. The model is valid in all regions of operation, and is developed using the quasi-two-dimensional approach. The hot-carrier-induced electron trapping in the oxide causes the channel shortening effect, which displays different behaviors for the device operated in the forward and reverse modes. It affects the threshold voltage reduction with channel length. This model incorporates the effects of velocity saturation, drain induced barrier lowering, channel length modulation, gate voltage induced mobility degradation, series source and drain resistances, and hot-carrier-induced oxide charges. The damaged channel region due to the fixed oxide charges trapped during hot-carrier injection is treated as a bias- and stress-time-dependent resistance. The resulting degraded BC MOSFET model is applicable for circuit simulation and its accuracy has been checked by the experimental data View full abstract»

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  • Lateral IGBT in thin SOI for high voltage, high speed power IC

    Page(s): 2251 - 2254
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    A high voltage LIGBT built in ultra-thin silicon-on-insulator (SOI) with a linearly graded doping profile is reported. The highest breakdown voltage of 720 V was measured for an LIGBT built in 0.5 μm SOI with a 4 μm buried oxide. A forward voltage drop of 6 V at 100 Acm-2 and a turn-off time of 140 ns have been achieved in the same device. Device forward voltage drop is very sensitive to the SOI thickness due to the recombination of carriers at the two silicon-silicon dioxide interfaces. An SOI thickness of 0.5 μm and an n-buffer doped to 1018 cm-3 have been found to be a reasonable trade-off between the breakdown voltage and the forward voltage drop View full abstract»

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  • Negative capacitance effect in semiconductor devices

    Page(s): 2196 - 2206
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    Nontrivial capacitance behavior, including a negative capacitance (NC) effect, observed in a variety of semiconductor devices, is discussed emphasizing the physical mechanism and the theoretical interpretation of experimental data. The correct interpretation of NC can be based on the analysis of the time-domain transient current in response to a small voltage step or impulse, involving a self-consistent treatment of all relevant physical effects (carrier transport, injection, recharging, etc.). NC appears in the case of the nonmonotonic or positive-valued behavior of the time-derivative of the transient current in response to a small voltage step. The time-domain transient current approach is illustrated by simulation results and experimental studies of quantum well infrared photodetectors (QWIPs). The NC effect in QWIPs has been predicted theoretically and confirmed experimentally. The huge NC phenomenon in QWIP's is due to the nonequilibrium transient injection from the emitter caused by the properties of the injection barrier and the inertia of the QW recharging View full abstract»

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  • A comparative analysis of the dynamic behavior of BTG/SOI MOSFETs and circuits with distributed body resistance

    Page(s): 2138 - 2145
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    To examine the dynamic nature of body-tied-to-gate (BTG) partially depleted SOI MOSFETs, CMOS inverter circuits (nine-stage ring oscillators and 50-stage chains) are simulated with SOISPICE, accounting for the BTG distributed body resistance. Due to the physical nature of the UFSOI model in SOISPICE, both the static and dynamic characteristics of the BTG device, contrasted to floating-body (FB) and body-tied-to-source (BTS) SOI MOSFETs, are faithfully revealed. Results give insight on previously measured, yet inadequately explained, dynamic behavior of the BTG device. Further, problematic hysteretic behavior associated with the dynamic operation of the device with realistic body sheet resistance is described, suggesting design constraints on the maximum device width. Finally, a performance assessment of the BTG device configuration in ultra-low-power CMOS digital applications is offered and compared with FB and BTS, indicating that the optimal configuration is in fact application-specific View full abstract»

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  • Gate current model for the hot-electron regime of operation in heterostructure field effect transistors

    Page(s): 2108 - 2115
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A model to describe the dependence of the gate current with source-to-drain voltage was developed and used to predict the performance of AlGaAs/InGaAs/GaAs HFETs. Our model describes the charge injection transistor (CHINT) regime of operation and account for real-space electron transport. In this model, the saturation of the hot-electron gate current is explained by the rapid drop in the energy relaxation time caused by the real-space transfer of electrons. Good correlation between the experimental and theoretical data was found for temperatures ranging from 198 to 398 K. Our experimental and theoretical results should be accounted for in the design of HFET devices and integrated circuits View full abstract»

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  • Effects of buffer layer structure on polysilicon buffer LOCOS for the isolation of submicron silicon devices

    Page(s): 2153 - 2160
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    The effects of a buffer layer structure on polysilicon buffered LOCOS were shown and analyzed. Sample wafers are classified into four groups to show the effect of the buffer layer structure. The structures of the four different buffer layers are monolayer polysilicon (typical), monolayer amorphous silicon (α-Si), double layer α-Si, and triple layer α-Si. Total buffer layer thickness of each structure is 60 nm. Structural analysis of the resultant samples was performed by using SEM, TEM, and SIMS. Sample with typical buffer structure shows not only rough surface morphology of bird's beak region but microtrenchings. By adopting the triple layer α-Si buffer structure (20 nm/20 nm/20 nm), we obtained smooth edge morphology and no microtrenchings. Leakage current of n+-p junction diode and gate oxide breakdown voltage of each sample were measured to check the effect of the buffer structure on PBL. Sample with the triple layer α-Si buffer structure shows the lowest junction leakage and the best gate oxide breakdown voltage characteristics. The electrical characteristics of the samples were consistent with the structural results View full abstract»

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  • A thorough investigation of the degradation induced by hot-carrier injection in deep submicron N- and P-channel partially and fully depleted unibond and SIMOX MOSFETs

    Page(s): 2146 - 2152
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    A thorough investigation of hot-carrier effects in deep submicron N- and P-channel SOI MOSFET's is reported in this paper. First, a comparison of device aging among three types of SOI devices fabricated by various technologies is shown. The carrier type, the quality of oxides, and the device structure are key parameters for the degradation mechanisms in these devices. On the other hand, the worst-case aging (V d=Vt,Vd/2 or Vd) also depends on these device distinctions. For fully depleted SOI MOSFETs, the variation of the main electrical parameters is determined with and without the influence of defects in the buried oxide. The device lifetime of NMOS/SOI in the worst-case condition is carefully predicted using accurate methods that take into account the degradation saturation and the region of defect creation (Si/SiO2 interface and/or oxide volume). Finally, an investigation of the aging/recovery mechanisms is carried out in P-channel SOI MOSFETs under an alternating stress View full abstract»

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  • Tunnelling transport in Al-n-GaSb Schottky diodes

    Page(s): 2247 - 2248
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    Investigations of Al Schottky contacts to n-GaSb are presented. Barrier heights of 0.60±0.02 eV are found. Forward bias ideality factors between 2 at 300 K to 60 at 10 K, are explained by electron tunneling. Ideality factors yield donor concentrations significantly greater than nominal, accentuated by annealing, suggesting modification of the reactive GaSb surface View full abstract»

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  • High efficiency polycrystalline silicon solar cells using low temperature PECVD process

    Page(s): 2131 - 2137
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    Conventionally directionally solidified (DS) and silicon film (SF) polycrystalline silicon solar cells are fabricated using gettering and low temperature plasma enhanced chemical vapor deposition (PECVD) passivation. Thin layer (~10 nm) of PECVD SiO2 is used to passivate the emitter of the solar cell, while direct hydrogen rf plasma and PECVD silicon nitride (Si3N4) are implemented to provide emitter and bulk passivation. It is found in this work that hydrogen rf plasma can significantly improve the solar cell blue and long wavelength responses when it is performed through a thin layer of PECVD Si3N4. High efficiency DS and SF polycrystalline silicon solar cells have been achieved using a simple solar cell process with uniform emitter, Al/POCl3 gettering, hydrogen rf plasma/PECVD Si3N4 and PECVD SiO2 passivation. On the other hand, a comprehensive experimental study of the characteristics of the PECVD Si3N4 layer and its role in improving the efficiency of polycrystalline silicon solar cells is carried out in this paper. For the polycrystalline silicon used in this investigation, it is found that the PECVD Si3N4 layer doesn't provide a sufficient cap for the out diffusion of hydrogen at temperatures higher than 500°C. Low temperature (⩽400°C) annealing of the PECVD Si3N 4 provides efficient hydrogen bulk passivation, while higher temperature annealing relaxes the deposition induced stress and improves mainly the short wavelength (blue) response of the solar cells View full abstract»

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  • Noise modeling in MESFET and HEMT mixers using a uniform noisy line model

    Page(s): 2207 - 2212
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    The aim of this paper is to present a noise model which predicts the noise performance of MESFET and HEMT mixers. The conversion and noise correlation matrices of a FET mixer are calculated using a uniform nonlinear noisy active line concept to describe the FET. This calculation is based on a perturbation analysis of the large-signal noiseless steady state, making it a “microscopic nonlinear noise model”. This method is applied to the case of a hot HEMT gate mixer and we show that the theoretical results are in agreement with experimental data View full abstract»

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  • Numerical analysis of device performance of metamorphic Iny Al1-yAs/InxGa1-xAs (0.3⩽x⩽0.6) HEMTs on GaAs substrate

    Page(s): 2089 - 2095
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    A numerical model describing the influence of InAs mole fraction on metamorphic HEMT structures (MM-HEMT) is proposed. The material properties are calculated using the Monte Carlo method, while the charge control law is calculated using a self-consistent solution of Poisson's and Schrodinger's equations. The modeling of the dc, ac, noise and high frequency performance of a device with 0.25-μm gate length is performed using the quasi-two-dimensional (Q2D) approach. This analysis shows that an InAs mole fraction of about 0.40 is an optimum composition for manufacturing high gain, low noise amplifiers. In this range of composition, the performance of MM-HEMT structures is similar to that obtained for lattice-matched HEMTs on InP substrates View full abstract»

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  • Avalanche multiplication noise characteristics in thin GaAs p+ -i-n+ diodes

    Page(s): 2102 - 2107
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    Avalanche noise measurements have been performed on a range of homojunction GaAs p+-i-n+ and n+-i-p + diodes with “i” region widths, ω from 2.61 to 0.05 μm. The results show that for ω⩽1 μm the dependence of excess noise factor F on multiplication does not follow the well-established continuous noise theory of McIntyre [1966]. Instead, a decreasing noise factor is observed as ω decreases for a constant multiplication. This reduction in F occurs for both electron and hole initiated multiplication in the thinner ω structures even though the ionization coefficient ratio is close to unity. The dead-space, the minimum distance a carrier must travel to gain the ionization threshold energy, becomes increasingly important in these thinner structures and largely accounts for the reduction in noise View full abstract»

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  • Self-aligned control of threshold voltages in sub-0.2-μm MOSFETs

    Page(s): 2161 - 2166
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    We propose a new method to control the threshold voltages (Vth) in sub-0.2 μm MOSFETs. The method suppresses Vth fluctuations caused by variations in the fabricated gate length. Our scheme is to change the concentration of the channel impurity according to the gate length by tilted ion implantation from two directions after the polysilicon gate formation. We show the feasibility of our process by two-dimensional (2-D) process and device simulations. Then we clarify that our scheme was realized in fabricated nMOSFETs. We also measured the Vth in numerous MOSFETs and show that our method can indeed suppress Vth fluctuations caused by variations in the fabricated gate length View full abstract»

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  • Generator of ultrashort optical pulses for time division multiplexing

    Page(s): 2122 - 2130
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    The performance of a device based on modified injection-locking techniques is studied by means of numerical simulations. The device incorporates master and slave configurations, each one with a DFB laser and an electroabsorption modulator (EAM). This arrangement allows the generation of high peak power, narrow optical pulses according to a periodic or pseudorandom bit stream provided by a current signal generator. The device is able to considerably increase the modulation bandwidth of free-running gain-switched semiconductor lasers using multiplexing in the time domain. Opportunities for integration in small packages or single chips are discussed View full abstract»

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  • Avalanche multiplication and breakdown in Ga0.52In0.48P diodes

    Page(s): 2096 - 2101
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    The electron and hole photomultiplication characteristics M, and M h have been measured in a series of Ga0.52In0.4xP devices with high field regions ranging from 2.0 μm down to the depletion width of a heavily doped p-n junction. The hole ionization coefficient β is found to be slightly higher than the electron ionization coefficient α at low fields but at high fields they approach one another. α and β are found to be significantly lower than in GaAs across the entire range of electric fields studied, and the breakdown voltage of Ga0.52 In0.48P is approximately 1.9 times higher than for similar GaAs structures. Contrary to the behavior observed in GaAs, the multiplication characteristics in all except the thinnest structures appear to be relatively unaffected by the dead space, the minimum distance required to gain sufficient energy to initiate impact ionization. In these very thin structures, a local description of multiplication cannot account for the ionization behavior accurately, and therefore, a Monte Carlo (MC) model has been used to reproduce the measured multiplication characteristics and extract the ionization coefficients View full abstract»

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  • A unified equilibrium treatment of modulation doped heterojunctions and grossly asymmetric homojunctions, and its application to MODFET design

    Page(s): 2187 - 2195
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    Homo- and hetero- “grossly asymmetric junctions”, i.e., “junctions between a heavily doped and a lightly doped layer”, are important building blocks of modern p+-i-n + and n+-i-n+ diodes, BJTs and MODFETs. We establish a hitherto unhighlighted aspect of the unity underlying the physics of these junctions, based on a simple yet original deduction from available surface field-potential relations. We show that, apart from pursuing the scientific quest for unification, the deduction also leads to three new results of practical significance. Firstly, simple expressions are obtained for important parameters of the space-charge layer of a general grossly asymmetric junction under equilibrium. These parameters include the width of the partially depleted region on the heavily doped side of the junction, that could not be obtained from earlier analyses. Secondly, applying this partial depletion width expression to the MODFET heterojunction, a nonlinear MODFET 2-DEG charge versus gate voltage model is derived, which is very useful for accurately simulating the effects of gradual saturation charge-voltage nonlinearity on dc and ac performance of analogue circuits. This charge-voltage model is expressed directly in terms of device parameters and temperature, unlike earlier nonlinear charge-voltage models whose parameters were empirical and could be extracted only by fitting to experimental data or complex numerical calculations. Thirdly, a new concept has emerged, as per which the effects of electron confinement, partial impurity ionization, Fermi-Dirac statistics and small geometry in a grossly asymmetric junction can be treated simply as apparent band discontinuity narrowing phenomena, and thus represented in an additive form by dimensionally identical parameters. The concept facilitates a comparison of different modulation doped heterojunction systems. We present calculations illustrating the above results View full abstract»

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  • Quantum effects upon drain current in a biased MOSFET

    Page(s): 2213 - 2221
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    In the past, classical device simulators have been modified to incorporate quantum effects using a quantum mechanical (QM) threshold-shift correction. In this way, it is hoped to retain accuracy without greatly complicating the simulation by incorporation of a coupled Schrodinger equation solver. In this work, the accuracy of this approach is checked for some specific examples. The drain current of heavily doped MOSFETs is found using a one-dimensional (1-D) Schrodinger-Poisson solver combined with a gradual channel model. Numerical results are compared to classical calculations augmented by the commonly proposed channel-current invariant QM threshold correction. Comparison of the two √Id(sat) versus VGS curves shows the same threshold shifts, but different slopes. The slope discrepancies are independent of substrate doping, and are largest for thin oxides. These differences are shown to be due to QM effects upon the surface potential gradient, a variation neglected in previous studies. To simplify device simulations, two simple quantum-effect corrections are proposed that show a great improvement in accuracy when compared to the earlier QM correction based on a channel-current invariant VG-shift View full abstract»

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  • Analytical gate current model for n-channel heterostructure field effect transistors

    Page(s): 2116 - 2121
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    A simple analytical gate current model for n-channel heterostructure field effect transistors (HFETs) has been developed. Our model is based on the self-consistent approximation to the solution of Schrodinger and Poisson's equations, and the theory of thermionic-field emission. Good agreement between the experimental data and the model results is obtained over the entire range of gate voltages, from below to above threshold, and over a wide range of temperature from 198 to 450 K. Only four parameters are used to fit the experimental data with two of these parameters obtained from the experimental results. This model is suitable for implementation in sophisticated CAD tools such as SPICE View full abstract»

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  • Improvement of the reliability of amorphous silicon transistors by conduction-band tail width reduction

    Page(s): 2179 - 2186
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    We present theoretical and experimental evidence showing that bias induced threshold voltage degradation of a-Si:H transistors is reduced by decreasing the width of the conduction-band tail. We show that transistors which are made using a thick (0.5 μm) a-Si:H layer possess a narrower conduction-band tail compared to transistors made using thin (0.05 μm) a-Si:H layers. We find that bias-induced threshold voltage degradation decreases by a factor of two for thick-layered TFTs compared with conventional, thin-layered TFTs. Finally, we present device design guidelines for improving the reliability of a-Si:H TFTs including several possible device designs for achieving further improvements in the reliability of a-Si:H TFTs View full abstract»

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  • A hierarchical reliability analysis for circuit design evaluation

    Page(s): 2254 - 2257
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    We suggest a computationally efficient and flexible strategy for assessment of reliability of integrated circuits. The concept of hierarchical reliability analysis proposed relies on doing reliability assessments during the design and layout process [reliability computer aided design (RCAD)]. Design rules are suggested based on calculations of steady-state mechanical stresses built up in interconnect graphs and trees due to electromigration. These design rules identify a large fraction of interconnect graphs in a typical design as immune to electromigration-induced failure. The stated design rules are an extension of the Blech-length concept to interconnect graphs. Our suggested new strategy will have important implications for design and layout processes as design limits for a given technology are reached View full abstract»

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  • A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot

    Page(s): 2249 - 2251
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    We have developed a new analytical ultra-short channel MOSFET model for circuit simulation including velocity overshoot effects. We have been able to reproduce experimental I-V curves and conductances of MOSFETs down to 0.07 μm channel lengths both at low and room temperatures View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology