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IEEE Transactions on Computers

Issue 9 • Date Sept. 1998

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Displaying Results 1 - 13 of 13
  • Comments on Duprat and Muller's branching CORDIC paper

    Publication Year: 1998, Page(s):1037 - 1040
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (72 KB)

    Duprat and Muller (IEEE trans. Computers, vo1.42. no. 2, p. 168-178, Feb. 1993) introduced the ingenious "Branching CORDIC" algorithm. It enables a fast implementation of CORDIC algorithm using signed digits and requires a constant normalization factor. This correspondence corrects some errors in the original paper. View full abstract»

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  • Double-basis multiplicative inversion over GF(2m)

    Publication Year: 1998, Page(s):960 - 970
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    Inversion over Galois fields is much more difficult than the corresponding multiplication. Efficient computation of inverses in GF(2 m) is considered by solving a set of linear equations over the ground field GF(2). The proposed algorithm uses two separate bases for the representation of its input and output elements and has low computational complexity. The algorithm is also suitable f... View full abstract»

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  • Multiple-valued signed digit adder using negative differential resistance devices

    Publication Year: 1998, Page(s):947 - 959
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (964 KB)

    The paper describes a signed digit full adder (SDFA) circuit consisting of resonant tunneling diodes (RTDs) and metal oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple valued logic literal circuit that utilizes the folded back I-V (or negative differential resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. ... View full abstract»

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  • Design of a high-speed square generator

    Publication Year: 1998, Page(s):1021 - 1026
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (260 KB)

    Given a binary number N, the simplest way for evaluating its square N2 is the use of ROM look-up tables. For example, the squares of 12-bit numbers can be stored in a ROM of (212×24) bits, which takes an area of 3.5 mm2 and an access time of 9.96 ns with 0.8 μm CMOS process. However, the conventional ROM table approaches are limited only for small bit size... View full abstract»

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  • A mechanically checked proof of the AMD5K86TM floating-point division program

    Publication Year: 1998, Page(s):913 - 926
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    We report on the successful application of a mechanical theorem prover to the problem of verifying the division microcode program used on the AMD5K86 microprocessor. The division algorithm is an iterative shift and subtract type. It was implemented using floating point microcode instructions. As a consequence, the floating quotient digits have data dependent precision. This breaks the c... View full abstract»

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  • Some topological properties of bitonic sorters

    Publication Year: 1998, Page(s):983 - 997
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (620 KB)

    The paper proves some topological properties of bitonic sorters, which have found applications in constructing, along with banyan networks, internally nonblocking switching fabrics in future broadband networks. The states of all the sorting elements of an N×N bitonic sorter are studied for four different input sequences {ai} i=lN, {bi}... View full abstract»

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  • Competitive on-line scheduling of imprecise computations

    Publication Year: 1998, Page(s):1027 - 1032
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (120 KB)

    The on-line scheduling of systems of imprecise computation tasks is investigated. The system objective is to maximize the value obtained. A formal model is defined. Under certain reasonable assumptions-formalized here as the weak feasible mandatory constraint-a competitive on-line scheduling algorithm is presented for the commonly studied uniform-density task systems. It is proven, however, that a... View full abstract»

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  • A new representation of elements of finite fields GF(2m) yielding small complexity arithmetic circuits

    Publication Year: 1998, Page(s):938 - 946
    Cited by:  Papers (33)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    Let F2 denote the binary field and F2m, an algebraic extension of degree m>1 over F2. Traditionally, elements of F2m are either represented as powers of a primitive element of F2m together with 0, or by an expansion in a basis of the vector space F2m over F2. We propose a new representation based on an isomorphism from... View full abstract»

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  • New Svoboda-Tung division

    Publication Year: 1998, Page(s):1014 - 1020
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    The paper presents a general theory for developing new Svoboda-Tung (or simply NST) division algorithms not suffering the drawbacks of the “classical” Svoboda-Tung (or simply ST) method. NST avoids the drawbacks of ST by proper recoding of the two most significant digits of the residual before selecting the most significant digit of this recoded residual as the quotient digit. NST reli... View full abstract»

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  • A fast and low cost self-routing permutation network

    Publication Year: 1998, Page(s):1033 - 1036
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    In this paper, we present a new implementation of the fast VLSI-efficient self-routing N×N permutation network proposed by Cam and Fortes, which requires only about half as much hardware and has a lower latency. Cam and Fortes' implementation uses Cormen and Leiserson's hyperconcentrators, which can route only active inputs. The reduction in hardware is achieved by modifying Cormen and Leise... View full abstract»

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  • Using decision diagrams to design ULMs for FPGAs

    Publication Year: 1998, Page(s):971 - 982
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (440 KB)

    Many modern field programmable logic arrays (FPGAs) use lookup table (LUT) logic blocks which can be programmed to realize any function of a fixed number of inputs. It is possible to employ logic blocks that realize only a subset of all functions, while the rest can be obtained by permuting and negating the inputs such blocks, known as Universal Logic Modules (ULMs), have already been considered f... View full abstract»

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  • Comparison of single- and dual-pass multiply-add fused floating-point units

    Publication Year: 1998, Page(s):927 - 937
    Cited by:  Papers (30)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Low power, low cost, and high performance factors dictate the design of many microprocessors targeted to the low power computing market. The floating point unit occupies a significant percentage of the silicon area in a microprocessor due its wide data bandwidth (for double precision computations) and the area occupied by the multiply array. For microprocessors designed for portable products, the ... View full abstract»

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  • Realizing common communication patterns in partitioned optical passive stars (POPS) networks

    Publication Year: 1998, Page(s):998 - 1013
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (520 KB)

    We consider the problem of realizing several common communication structures in the all-optical Partitioned Optical Passive Stars (POPS) topology. We show that, often, the obvious or “natural” method of implementing a communication pattern in the POPS does not efficiently utilize its communication capabilities. We present techniques which distribute the communication load uniformly in ... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org