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Consumer Electronics, IEEE Transactions on

Issue 3 • Date Aug. 1998

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Displaying Results 1 - 25 of 102
  • A DCT-based Embedded Image Coder Using Wavelet Structure Of DCT For Very Low Bit Rate Video Codec

    Publication Year: 1998 , Page(s): 500 - 508
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1828 KB)  

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  • A portable Java API interface to simplify user access to digital cameras

    Publication Year: 1998 , Page(s): 686 - 691
    Cited by:  Papers (3)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    The digital camera is one of the main successes in consumer electronics. However a typical digital camera remains tied to proprietary software on a personal computer. In this paper we describe the design and implementation of a portable Java API to simplify end user access to digital cameras and to provide interconnectivity with a new generation of intelligent home appliances View full abstract»

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  • Real-time implementation of the MPEG-2 audio codec on a DSP

    Publication Year: 1998 , Page(s): 866 - 871
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (512 KB)  

    This paper presents the implementation of MPEG-2 layer 1 audio coding and decoding system on a general purpose fixed-point DSP chip. A modified coding algorithm that alleviates the edge effect is described. This scheme encodes data in frames adjacent to the current frame so that data is closely correlated between frames. Results from the DSP real-time implementation are examined. Bit-rates from 74 to 138 kbps for the signals tested are attainable with transparent quality signal reconstruction View full abstract»

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  • A digital vestigial-sideband (VSB) channel decoder IC for digital TV

    Publication Year: 1998 , Page(s): 811 - 816
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    This paper describes an integrated 8-VSB demodulator-decoder IC (TDA8960) which can receive digital TV (DTV) signals that are formatted according to the ATSC standard View full abstract»

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  • MPEG-1 audio real-time encoding system

    Publication Year: 1998 , Page(s): 888 - 894
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (524 KB)  

    MPEG technology is commonly used by multimedia equipment. We have developed an MPEG camera (Imaide et al. 1997; Asada et al. 1997) that compresses video and audio in real-time. The hardware or DSP has been used to encode/decode MPEG audio, one of the key technologies in MPEG, when real-time processing is required. However, as the MPEG camera is for consumer use, it needs to be compact and light. We have developed a software system with a system CPU to encode and decode the MPEG audio in real-time to satisfy the requirement of the entire camera system View full abstract»

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  • User interface technologies for home appliances and networks

    Publication Year: 1998 , Page(s): 679 - 685
    Cited by:  Papers (14)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (928 KB)  

    The design and implementation of portable, lightweight user-interfaces to provide access to remote embedded home-systems and home-networks is described. This paper is focussed on emerging standards in the consumer electronics field, including embedded-Java, the handheld device markup language (HDML) and remote frame buffer (RFB) protocol technology as implemented in the public-domain virtual network computer (VNC) software. A key goal of the present paper is to provide an objective technical assessment of the applicability of each of these technologies to the development of practical consumer appliances and handheld terminals providing enhanced user access to the home environment View full abstract»

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  • A simple algorithm for the reduction of blocking artifacts in images and its implementation

    Publication Year: 1998 , Page(s): 1062 - 1070
    Cited by:  Papers (18)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1384 KB)  

    A simple but effective operator for the reduction of blocking artifacts is presented, together with a simple hardware implementation. The method is based on the rational filter approach: the operator is expressed as a ratio between a linear and a polynomial function of the input data. Such filters have been proved to outperform other conventional methods in other applications, such as noise smoothing, thanks to their capability of adapting gradually to the local image characteristics. The filter is capable of biasing its behaviour in order to achieve good performance both in uniform areas, where linear smoothing is needed, and in textured zones, where nonlinear and directional filtering is required. An activity detector is embedded in the expression of the operator itself so that the biasing of the behaviour of the filter is smooth and not based on fixed thresholds. A solution for the hardware implementation of the scheme is presented in detail. Despite the simplifications imposed by the hardware design, the filter retains the same efficiency as the original algorithm View full abstract»

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  • A VLSI implementation of a reconfigurable rational filter

    Publication Year: 1998 , Page(s): 1076 - 1085
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1132 KB)  

    We propose an implementation of a reconfigurable system which exploits the features and the robustness of rational filters in order to accomplish various image processing tasks. This particular architecture is able to implement various different algorithms as noise-smoothing edge preserving filtering, interpolation, blocking artifacts removal. The architecture is structured as a bit-level pipeline and can work at frequency of 200 MHz, maintaining a quite small size of 7×5 mm2 View full abstract»

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  • Perfect flat CRT discussed from a standpoint of “viewing performance”

    Publication Year: 1998 , Page(s): 712 - 717
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    This paper describes features of the perfect flat CRT as well as major technologies used to realize it. An analysis of the relationship between viewer's eye point and picture distortion is done, using computers to show that the perfect flat CRT is ideal as a display device because no picture distortion occurs regardless of viewer's eye point, and an object moving on the CRT screen can be viewed with no distortion regardless of its location on the screen. Also, the developed tempered glass bulb technology is discussed as one of major innovations necessary in realizing this perfect flat CRT View full abstract»

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  • Regularized iterative image interpolation and its application to spatially scalable coding

    Publication Year: 1998 , Page(s): 1042 - 1047
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1468 KB)  

    This paper presents a regularized iterative image interpolation algorithm, which can restore high frequency details in the original high resolution image. In order to apply the regularization approach to the interpolation procedure, we first present a two-dimensional separable image degradation model for a low resolution imaging system. According to the model, we propose a regularization based spatial image sequence interpolation algorithm and apply the proposed algorithm to a spatially scalable coding View full abstract»

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  • Front-end of a digital ATV receiver

    Publication Year: 1998 , Page(s): 817 - 822
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    This paper describes the front-end of a digital ATV receiver. The front-end contains a tuner, a surface acoustic wave (SAW) filter, a downconverter, a vestigial sideband (VSB) demodulator, an analog-to-digital converter (ADC), and an on-board microprocessor. The signal level at the input of the ATV receiver, in the case of a terrestrial broadcast, can change by more than 80 dB. The level of the input signal can change rapidly due to plane jitter or dynamic ghost interference. The performance of the ATV receiver depends heavily on the accuracy and reaction time of the automatic gain control (AGC) system. The concept and algorithm for a digital delayed AGC was developed and investigated. A digital delayed AGC algorithm was implemented using an on-board microprocessor with data supplied by the VSB demodulator's AGC output. The front-end board was tested in the lab and in the field with real terrestrial ATV broadcasts and some of the results are presented View full abstract»

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  • VLSI architecture of signal processing chip set for 42-inch DC PDP HDTV receiver

    Publication Year: 1998 , Page(s): 698 - 703
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (780 KB)  

    A signal processing chip set for 42-inch DC PDP HDTV receivers has been developed. Four kinds of signal processing LSIs are fabricated with a semi-custom LSI design and 0.35 μm triple-metal CMOS technology. This paper describes the architecture of the LSI chip set and new circuit configurations to improve the picture quality. The chip set has enabled a practical PDP HDTV receiver to be fabricated View full abstract»

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  • An analog-to-digital processor for camcorders and digital still cameras

    Publication Year: 1998 , Page(s): 570 - 580
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    High performance commercial imaging systems, such as camcorders and digital still cameras, employ charge-coupled devices to convert light energy to electrical signals. The output from the CCD requires automatic gain control before it can be applied to an analog-to-digital (A/D) converter where digitization takes place. Other processing is also required for viewing the output of the recorded image. The development described is an integrated circuit that contains many of the key features associated with processing the analog signals within a camcorder or a digital still camera View full abstract»

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  • CCD noise filtering based on 3-dimensional nonlinear partial differential equation

    Publication Year: 1998 , Page(s): 1086 - 1090
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (612 KB)  

    A three dimensional anisotropic diffusion equation is proposed to remove noise in video sequences. The three dimensional anisotropic diffusion equation utilizes the fact that consecutive frames of high correlation can be obtained in video sequences. It is shown that the three dimensional diffusion equation gives better results than the two dimensional diffusion equation which only deals with still images and slowly smoothes the edge boundaries View full abstract»

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  • 3D digital broadcasting system and IRD using progressive scanned digital broadcasting

    Publication Year: 1998 , Page(s): 1169 - 1172
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    This paper describes the newly developed 3D digital broadcasting system and the IRD (Integrated Receiver and Decoder) enabling the broadcast of the 3D images using high-definition progressive scanned digital broadcasting with additional simple functions View full abstract»

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  • Set top performance benchmarking as a system design tool

    Publication Year: 1998 , Page(s): 841 - 850
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    A benchmark is a tool to evaluate system performance before and after a product has been designed. This paper addresses a series of theoretical benchmarks for the design of digital set top box architectures View full abstract»

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  • Mapping home-network appliances to TCP/IP sockets using a three-tiered home gateway architecture

    Publication Year: 1998 , Page(s): 729 - 736
    Cited by:  Papers (13)  |  Patents (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (744 KB)  

    A three-tier gateway architecture for internetworking between home automation networks and a TCP/IP based wide area network, such as the Internet, is described. The architecture abstracts the functionality of any home network into a driver layer (tier one), and provides a common access layer (tier two) from any TCP/IP network application (tier three) to a local home automation network. Clients and application programs may transparently access services and resources on the home network and appliances connected to the home network may access resources and services on the TCP/IP network View full abstract»

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  • Bit allocation method for AC-3 encoder

    Publication Year: 1998 , Page(s): 883 - 887
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (464 KB)  

    Dolby AC-3 is an audio coder selected in the United States high definition television (HDTV) standards and widely adopted for the audio codec in DVD films. For audio codecs, the complexity of the audio encoders is always higher than that of the decoders. The main module leading to the higher complexity is the bit allocation process. The objective of the bit allocation is to allocate restricted bits to encoded information. Since the AC-3 coder has adopted a floating point representation which the magnitude of each spectral line is represented with an exponent and a mantissa, the bit allocation process not only has to decide the suitable quantization method for the mantissa similar to the process in other coding standards such as MPEG 1, but also the exponent strategies and hence the parameters in psychoacoustic models. This coding process has been referred to as a hybrid coding (Todd et al. 1994) and has led to immense complexity for an encoder. This paper proposes an efficient method for the bit allocation process View full abstract»

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  • Low phase noise and low intermodulation analog front-end for an OFDM system

    Publication Year: 1998 , Page(s): 1001 - 1011
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    We have newly developed an analog front-end with low phase noise, low intermodulation and high linearity characteristics which is applicable to an OFDM system. The double conversion architecture using the GaAs mixer ICs, a low phase noise local oscillator construction and a delayed gain control system are discussed View full abstract»

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  • An integrated DTV receiver for ATSC digital television standard

    Publication Year: 1998 , Page(s): 667 - 671
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    This paper describes a system structure of a DTV receiver capable of decoding a terrestrial broadcast signal which conforms to the ATSC digital television standard. A newly developed chip set is used to realize a compact decoder unit View full abstract»

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  • Performance of the Viterbi decoder for DVB-T in Rayleigh fading channels

    Publication Year: 1998 , Page(s): 994 - 1000
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (520 KB)  

    We present the performance of the Viterbi decoder using the soft decision method for the European digital video broadcasting for terrestrial (DVB-T) specification in Rayleigh fading channels. We investigate the bit error rate (BER) performance of the Viterbi decoder for hard and soft decisions in terms of the decoding depth and the number of allocated bits for the soft decision. We also consider the decoder performance in the Doppler shift. The simulation results show that the Viterbi decoder with 5-bit decision and the decoding depth of 55 is a sub-optimum decoder View full abstract»

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  • The set-top box as “multi-media terminal”

    Publication Year: 1998 , Page(s): 833 - 840
    Cited by:  Papers (12)  |  Patents (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (832 KB)  

    The current platform for digital television services in Germany, the “d-box”, based on the DVB/MPEG-2 standards provides the technical basis for the handling of services. With the integrated modem, SCART, and SCSI-2 interfaces, the d-box offers two service classes: video/audio services, and data services. This paper discusses important technical consumer and commercial aspects of providing services over satellite and cable involving both a TV and a PC connected to a “multimedia” terminal View full abstract»

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  • Mutual interference between adjacent analog scrambled signal and 64QAM signal in CATV system

    Publication Year: 1998 , Page(s): 944 - 951
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (672 KB)  

    The mutual interference between an analog synchronised pulse compressed signal and an adjacent 64QAM signal, experimental results, the cause of the interference, and characteristics of the equipment used were described View full abstract»

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  • VLSI implementation of visual block pattern truncation coding

    Publication Year: 1998 , Page(s): 490 - 499
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (728 KB)  

    The paper proposes a pipelined architecture of a visual block pattern truncation coding algorithm to minimize the mean square error. Using this chip, the VBPTC based system can be applied to real-time encoding for moving pictures View full abstract»

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  • Real-time 2-3 pull-down elimination applying motion estimation/compensation in a programmable device

    Publication Year: 1998 , Page(s): 930 - 938
    Cited by:  Papers (34)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    A software package realizes real-time video processing on a commercially available programmable device. The software implements a motion estimator and a picture rate convertor to provide judder-free display of movie material broadcast in 2-3 pull-clown mode. A new object-based true-motion estimation algorithm efficiently uses the VLIW core of the processor. It permits quasi-simultaneous motion estimation/segmentation for a fixed maximum number of objects View full abstract»

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Aims & Scope

The main focus for the IEEE Transactions on Consumer Electronics is the engineering and research aspects of the theory, design, construction, manufacture or end use of mass market electronics, systems, software and services for consumers.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Simon Sherratt, IEEE Fellow
Professor of Consumer Electronics
School of Systems Engineering
The University of Reading
Reading, Berkshire RG6 6AY  U.K.
r.s.sherratt@reading.ac.uk; sherratt@ieee.org
Phone:+44 (0) 118 3788588