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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Issue 3 • Date Sept. 1998

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VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration

Computing support-minimal subfunctions during functional decomposition

High-performance automatic target recognition through data-specific VLSI

High-speed CMOS switch designs for free-space optoelectronic MIN's

Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties

Mesh routing topologies for multi-FPGA systems

On chip testing data converters using static parameters

Bounds on pseudoexhaustive test lengths

On methods to match a test pattern generator to a circuit-under-test

Effect of the prefabricated routing track distribution on FPGA area-efficiency

Analytic termination metrics for pin-to-pin lossy transmission lines with nonlinear drivers

Wave-pipelining: a tutorial and research survey

Efficient VLSI for Lempel-Ziv compression in wireless data communication networks

Efficient statistical approach to estimate power considering uncertain properties of primary inputs

Low-power arithmetic for the processing of video signals

Routability improvement using dynamic interconnect architecture

Automatic generation of error control codes for computer applications

Testability analysis and behavioral testing of the Hopfield neural paradigm

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