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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date Jul 1998

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Displaying Results 1 - 10 of 10
  • A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET

    Publication Year: 1998 , Page(s): 631 - 638
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    A charge/capacitance model of a simple form that is continuous across the linear and saturation regimes is developed. The model is based on a conductance analysis of the MOSFET which incorporates velocity saturation at a first-principles level. By relating charge layers within the device to characteristics of the conductance, the charge model not only is able to characterize C-V behavior but to also incorporate velocity saturation. Since the basic conductance form is a hyperbola, the model is mathematically simple and robust and yields MOSFET capacitances and charges which are continuous and of infinite differentiability over the linear and saturation regimes of device operation View full abstract»

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  • Computing observability don't cares efficiently through polarization

    Publication Year: 1998 , Page(s): 573 - 581
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    A new method is presented to compute the exact observability don't cares (ODCs) for multiple-level combinational circuits. A new mathematical concept, called polarization, is introduced. Polarization captures the essence of ODC calculation on the otherwise difficult points of reconvergence. It makes it possible to derive the ODC of a node from the ODCs of its fanouts with a very simple formula. Experimental results for the 39 largest MCNC benchmark examples show that the method is able to compute the ODC set (expressed as a Boolean network) for all but one circuit in at most a few seconds View full abstract»

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  • Using cone structures for circuit partitioning into FPGA packages

    Publication Year: 1998 , Page(s): 592 - 600
    Cited by:  Papers (5)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    Circuit designers and high-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many I-Os. This problem becomes more frequent with field-programmable gate arrays (FPGAs) which commonly have small size limits and up to ten times smaller I-O pin limits. An I-O bottleneck often occurs which during circuit partitioning means more required packages and more ordinary signal wires crossing between the packages. More critical timing paths between packages are cut and circuit operational frequencies are drastically reduced. In this paper, two new partitioning algorithms are presented that use cone structures to partition large hierarchical blocks into FPGA's. Cone structures are minimum cut partitioning structures for netlists with low fanout, and clustering structures for partitioning netlists with high fanout. Cone structures also allow for full containment of critical paths. When used with good merging and cutting strategies, results show the cone partitioning algorithms given here produces fewer FPGG partitions than min-cut with good performance View full abstract»

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  • Direct mapping of RTL structures onto LUT-based FPGA's

    Publication Year: 1998 , Page(s): 624 - 631
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    The problem of mapping synthesized RTL structures onto look-up table (LUT)-based field programmable gate arrays (FPGAs) is addressed in this paper. The key distinctive feature of this work is a novel approach to perform the mapping by utilizing the iterative nature of the data path components. The approach exploits the regularity of data path components by slicing the components and mapping slices of one or more connected components together. This is in contrast to other FPGA mapping techniques which start from Boolean networks. Both cost optimal and delay optimal mappings are supported. The objective in cost optimal mapping is to cover a given data path network with minimum number of CLBs. Similarly in delay optimal mapping, the objective is to reduce the number of CLB levels in the critical combinational logic paths. Implementation of these mapping techniques with LUT based FPGAs as target technology results in a significant reduction in cost (CLB count) and critical path delays (CLB levels) View full abstract»

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  • Code density optimization for embedded DSP processors using data compression techniques

    Publication Year: 1998 , Page(s): 601 - 608
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    Code-size minimization in embedded systems is an important problem because code size directly affects production cost. We address the problem of code compression in systems with embedded DSP processors. We use data-compression methods to develop code-size minimization strategies. In our framework, the compressed program consists of a skeleton and a dictionary. We show that the dictionary can be computed by solving a set-covering problem derived from the original program. We also address performance considerations, and show that they can be incorporated easily into the set-covering formulation. Experimental results are presented View full abstract»

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  • A note on computing a maximal planar subgraph using PQ-trees

    Publication Year: 1998 , Page(s): 609 - 612
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    The problem of computing a maximal planar subgraph of a nonplanar graph has been deeply investigated over the last 20 years. Several attempts have been tried to solve the problem with the help of PQ-trees. The latest attempt has been reported by Jayakumar et al. In this paper we show that the algorithm presented by Jayakumar et al. is not correct. We show that it does not necessarily compute a maximal planar subgraph and we note that the same holds for a modified version of the algorithm presented by Kant. Our conclusions most likely suggest not to use PQ-trees at all for this specific problem View full abstract»

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  • Preservation of passivity during RLC network reduction via split congruence transformations

    Publication Year: 1998 , Page(s): 582 - 591
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    Resistance-inductance-capacitance (RLC) network reduction refers to the formulation of small networks whose port behavior is similar to that of large RLC networks. Several network reduction algorithms have been developed in the last few years, but none exist for RLC networks which preserve passivity. The loss of passivity can be a serious problem because simulations of the reduced networks may encounter artificial oscillations or “time step too small” errors which render the simulations useless. This paper presents a set of well-conditioned transformations called “split congruence transformations” (SCTs) which can he used to preserve specified moments and resonances for RLC network reduction, and these transformations are proven to preserve passivity. Network reduction examples are provided to demonstrate the utility of SCTs View full abstract»

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  • Machine learning-based VLSI cells shape function estimation

    Publication Year: 1998 , Page(s): 613 - 623
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (300 KB)  

    We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neural network that predicts the number of contacts (vias) to produce estimates of cell layout shape functions. We have experimented with this approach on an independent test set of circuits and the results are very encouraging. The resulting estimation system is very fast and can be easily incorporated into exiting floorplanning systems. An additional benefit of the the machine learning aspect is the simplicity and systematicity in incorporating into the estimation system new circuits and technology information as they become available View full abstract»

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  • Mixed-element decomposition method for three-dimensional grid adaptation

    Publication Year: 1998 , Page(s): 561 - 572
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    A new method for adaptive tessellation of three-dimensional (3-D) grids is presented. A mixed-element decomposition method is introduced for local refinement of fully unstructured grids, consisting of tetrahedra and octahedra. The method preserves the shape of the elements of the initial grid and therefore the element quality. Furthermore, local anisotropies of the initial grid are preserved. The developed implementation allows efficient adaptation and is used in a finite element program for simulation of thermal diffusion processes View full abstract»

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  • An interpolated flux scheme for cellular automaton device simulation

    Publication Year: 1998 , Page(s): 553 - 560
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Cellular automaton (CA)-based device simulation is one of the most powerful tool to solve Boltzmann transport equation (BTE) of carriers in semiconductor devices. In comparison to the Monte Carlo (MC) method which suffers statistical noise problems, cell representation used in the CA method realizes noise free analysis of the carrier distribution function (DF) both in real and momentum space. However, CA requires more computer resources than MC in typical cases because cell sizes used for both real and momentum space are restricted to be small enough not to cause artificial diffusion (ADF). In this paper, a new scheme for calculation of flux among cells is proposed in which carrier distribution is interpolated between neighbor cells. The suppression of ADF is confirmed through comparisons to other simulation methods in homogeneous cases, an n+-p diode case and an n+-n-n+ structure case. Consistency with MC analysis is also demonstrated by analyzes of homogeneous cases and an n +-n-n+ case and also by a theoretical study. A speed up of at least two orders of magnitude can be obtained by introducing the new flux calculation whose accuracy is ensured with much less number of cells than conventional CA methods. Consequently, this CA method is drastically improved as a practical tool for semiconductor device modeling from the point of CPU time and accuracy View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu