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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Date Jul 1998

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Displaying Results 1 - 10 of 10
  • A simple, continuous, analytical charge/capacitance model for the short-channel MOSFET

    Publication Year: 1998, Page(s):631 - 638
    Cited by:  Papers (2)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    A charge/capacitance model of a simple form that is continuous across the linear and saturation regimes is developed. The model is based on a conductance analysis of the MOSFET which incorporates velocity saturation at a first-principles level. By relating charge layers within the device to characteristics of the conductance, the charge model not only is able to characterize C-V behavior but to al... View full abstract»

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  • Using cone structures for circuit partitioning into FPGA packages

    Publication Year: 1998, Page(s):592 - 600
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    Circuit designers and high-level synthesis tools have traditionally used circuit hierarchy to partition circuits into packages. However hierarchical partitioning can not be easily performed if hierarchical blocks have too large a size or too many I-Os. This problem becomes more frequent with field-programmable gate arrays (FPGAs) which commonly have small size limits and up to ten times smaller I-... View full abstract»

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  • Computing observability don't cares efficiently through polarization

    Publication Year: 1998, Page(s):573 - 581
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (296 KB)

    A new method is presented to compute the exact observability don't cares (ODCs) for multiple-level combinational circuits. A new mathematical concept, called polarization, is introduced. Polarization captures the essence of ODC calculation on the otherwise difficult points of reconvergence. It makes it possible to derive the ODC of a node from the ODCs of its fanouts with a very simple formula. Ex... View full abstract»

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  • An interpolated flux scheme for cellular automaton device simulation

    Publication Year: 1998, Page(s):553 - 560
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (172 KB)

    Cellular automaton (CA)-based device simulation is one of the most powerful tool to solve Boltzmann transport equation (BTE) of carriers in semiconductor devices. In comparison to the Monte Carlo (MC) method which suffers statistical noise problems, cell representation used in the CA method realizes noise free analysis of the carrier distribution function (DF) both in real and momentum space. Howe... View full abstract»

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  • Code density optimization for embedded DSP processors using data compression techniques

    Publication Year: 1998, Page(s):601 - 608
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Code-size minimization in embedded systems is an important problem because code size directly affects production cost. We address the problem of code compression in systems with embedded DSP processors. We use data-compression methods to develop code-size minimization strategies. In our framework, the compressed program consists of a skeleton and a dictionary. We show that the dictionary can be co... View full abstract»

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  • Preservation of passivity during RLC network reduction via split congruence transformations

    Publication Year: 1998, Page(s):582 - 591
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (264 KB)

    Resistance-inductance-capacitance (RLC) network reduction refers to the formulation of small networks whose port behavior is similar to that of large RLC networks. Several network reduction algorithms have been developed in the last few years, but none exist for RLC networks which preserve passivity. The loss of passivity can be a serious problem because simulations of the reduced networks may enc... View full abstract»

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  • Direct mapping of RTL structures onto LUT-based FPGA's

    Publication Year: 1998, Page(s):624 - 631
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (240 KB)

    The problem of mapping synthesized RTL structures onto look-up table (LUT)-based field programmable gate arrays (FPGAs) is addressed in this paper. The key distinctive feature of this work is a novel approach to perform the mapping by utilizing the iterative nature of the data path components. The approach exploits the regularity of data path components by slicing the components and mapping slices... View full abstract»

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  • Machine learning-based VLSI cells shape function estimation

    Publication Year: 1998, Page(s):613 - 623
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (300 KB)

    We describe in this paper a novel approach based upon machine learning for estimating layout shape functions of full-custom integrated circuit cells. A neural network is trained to estimate one dimension of cell layout from circuit netlist, a desired packing density, and prescribed values of the complementary dimension. The neural network is then combined with a linear function generator and a neu... View full abstract»

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  • Mixed-element decomposition method for three-dimensional grid adaptation

    Publication Year: 1998, Page(s):561 - 572
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (308 KB)

    A new method for adaptive tessellation of three-dimensional (3-D) grids is presented. A mixed-element decomposition method is introduced for local refinement of fully unstructured grids, consisting of tetrahedra and octahedra. The method preserves the shape of the elements of the initial grid and therefore the element quality. Furthermore, local anisotropies of the initial grid are preserved. The ... View full abstract»

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  • A note on computing a maximal planar subgraph using PQ-trees

    Publication Year: 1998, Page(s):609 - 612
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The problem of computing a maximal planar subgraph of a nonplanar graph has been deeply investigated over the last 20 years. Several attempts have been tried to solve the problem with the help of PQ-trees. The latest attempt has been reported by Jayakumar et al. In this paper we show that the algorithm presented by Jayakumar et al. is not correct. We show that it does not necessarily compute a max... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu