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IEEE Transactions on Computers

Issue 7 • July 1998

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Displaying Results 1 - 11 of 11
  • Special Section Referee List

    Publication Year: 1998, Page(s): 787
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    Freely Available from IEEE
  • A priori worst case error bounds for floating-point computations

    Publication Year: 1998, Page(s):750 - 756
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    A new technique for the a priori calculation of rigorous error bounds for floating-point computations is introduced. The theorems given in the paper combined with interval arithmetic lead to the implementation of reliable software routines, which enable the user to compute the desired error bounds automatically by a suitable computer program. As a prominent example, a table-lookup algorithm for ca... View full abstract»

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  • CORDIC vectoring with arbitrary target value

    Publication Year: 1998, Page(s):736 - 749
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (532 KB)

    The computation of additional functions in the CORDIC module increases its flexibility. We consider here the extension of the vectoring mode (angle calculation) so that the vector is rotated until one of the coordinates (for instance y) attains a target value t (in contrast to the value 0, as in standard vectoring). The main problem in the algorithm is that the modulus of the vector is scaled in e... View full abstract»

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  • Long and fast up/down counters

    Publication Year: 1998, Page(s):722 - 735
    Cited by:  Papers (34)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1056 KB)

    This paper presents recent advances in the design of constant-time up/down counters in the general context of fast counter design. An overview of existing techniques for the design of long and fast counters reveals several methods closely related to the design of fast adders, as well as some techniques that are only valid for counter design. The main idea behind the novel up/down counters is to re... View full abstract»

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  • Papers from the 13th IEEE Symposium on Computer Arithmetic

    Publication Year: 1998, Page(s): 721
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (36 KB)

    First Page of the Article
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  • Asynchronous comparison-based decoders for delay-insensitive codes

    Publication Year: 1998, Page(s):802 - 811
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A comparison-based decoder detects the arrival of a code word by comparing the received checkbits with the checkbits computed using the received data. Implementation issues underlying comparison-based decoders for systematic delay-insensitive (DI) or unordered codes is the subject of this paper. We show that if the decoder is to be implemented using asynchronous logic, i.e., if the gate and wire d... View full abstract»

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  • CAM2: a highly-parallel two-dimensional cellular automaton architecture

    Publication Year: 1998, Page(s):788 - 801
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1392 KB)

    Cellular automaton (CA) is a promising computer paradigm that can break through the von Neumann bottleneck. Two-dimensional CA is especially suitable for application to pixel-level image processing. Although various architectures have been proposed for processing two-dimensional CA, there are no compact, practical computers. So, in spite of its great potential, CA is not widely used: This paper pr... View full abstract»

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  • Arithmetic co-transformations in the real and complex logarithmic number systems

    Publication Year: 1998, Page(s):777 - 786
    Cited by:  Papers (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    The real logarithmic number system, which represents a value with a sign bit and a quantized logarithm, can be generalized to create the complex logarithmic number system, which replaces the sign bit with a quantized angle in a log/polar coordinate system. Although multiplication and related operations are easy in both real and complex systems, addition and subtraction are hard, especially when in... View full abstract»

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  • Exponentiation using division chains

    Publication Year: 1998, Page(s):757 - 765
    Cited by:  Papers (10)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    Exponentiation may be performed faster than the traditional square and multiply method by iteratively reducing the exponent module numbers which, as exponents themselves, require few multiplications. This mainly includes those with few nonzero bits. For a suitable choice of such divisors, the resulting mixed basis representation of the exponent reduces the expected number of nonsquaring multiplica... View full abstract»

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  • Pfair scheduling of generalized pinwheel task systems

    Publication Year: 1998, Page(s):812 - 816
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    The scheduling of generalized pinwheel task systems is considered. It is shown that pinwheel scheduling is closely related to the fair scheduling of periodic task systems. This relationship is exploited to obtain new scheduling algorithms for generalized pinwheel task systems. When compared to traditional pinwheel scheduling algorithms, these new algorithms are both more efficient from a run-time ... View full abstract»

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  • An RNS Montgomery modular multiplication algorithm

    Publication Year: 1998, Page(s):766 - 776
    Cited by:  Papers (51)  |  Patents (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    We present a new RNS modular multiplication for very large operands. The algorithm is based on Montgomery's method adapted to mixed radix, and is performed using a residue number system. By choosing the moduli of the RNS system reasonably large and implementing the system on a ring of fairly simple processors, an effect corresponding to a redundant high-radix implementation is achieved. The algori... View full abstract»

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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org