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IEE Proceedings - Computers and Digital Techniques

Issue 4 • Date Jul 1998

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Displaying Results 1 - 11 of 11
  • Correspondence on `Planar constrained terminals over-the-cell router'

    Publication Year: 1998, Page(s):319 - 320
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (128 KB)

    A new routing model with constrained terminal structure for over-the-cell channel routing and a graph theoretical algorithm for solving the planar constrained terminals over-the-cell routing problem have recently been published. The routing model with constrained terminal structure assigns the connection constraint between adjacent layers on terminals and makes use of the vacant locations on each ... View full abstract»

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  • Efficient algorithm and architecture for scan conversion in HDTV

    Publication Year: 1998, Page(s):287 - 291
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (880 KB)

    The main objective of this paper is to develop an efficient algorithm and architecture for scan conversion in high definition television. Scan conversion requires rapid operations of a large amount of image signal data, thus complex algorithm, architecture, and a large memory are necessary. A simple and effective interpolation method and a pipelined parallel architecture using memory partitioning ... View full abstract»

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  • Fault-tolerant scaleable multicast algorithm with piggybacking approach on logical process ring

    Publication Year: 1998, Page(s):292 - 300
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (972 KB)

    A novel reliable, totally ordered multicast protocol on a single logical process ring (called FTSM) is presented. It guarantees totally ordered and atomic delivery of multicast messages in the presence of message loss, site crashes and network partitioning. By placing sequence numbers on messages, a process holding a virtual token multicasts totally ordered messages. Atomic delivery of multicast m... View full abstract»

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  • Partial scan design based on levelised combinational structure

    Publication Year: 1998, Page(s):249 - 254
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. A `combinational structure' has been developed to avoid the use of a sequential test generator. But test patterns shifted on the scan register have to be held for a sequential depth period upon the aid of the dedi... View full abstract»

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  • Sensitisable-path-oriented clustered voltage scaling technique for low power

    Publication Year: 1998, Page(s):301 - 307
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (644 KB)

    Because the average power consumption of CMOS digital circuits is proportional to the square of the supplied voltage, a clustered voltage scaling (CVS) technique has previously been proposed to reduce power without sacrificing the circuit performance. In this paper the authors propose a path-oriented CVS algorithm, which can take the false paths into account. Extensive experiments are conducted on... View full abstract»

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  • Parallelism exploitation in superscalar multiprocessing

    Publication Year: 1998, Page(s):255 - 264
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (868 KB)

    To exploit more parallelism in programs, superscalar multiprocessor systems, which exploit both fine-grained and coarse-grained parallelism, have been the trend in designing high-speed computing systems. Recently, the authors have developed a simulator for evaluating superscalar multiprocessor systems. This simulator models both a superscalar processor that can exploit instruction-level parallelis... View full abstract»

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  • Algebraic test-pattern generation based on the Reed-Muller spectrum

    Publication Year: 1998, Page(s):308 - 316
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (888 KB)

    In the last few years new test generation procedures based on Boolean techniques have been reported. Despite the fact that Boolean operations are in general computationally expensive and that procedures are available based on path-oriented methods of reasonable efficiency, there is still interest in developing new methods to speed up the detection of those faults that are hard to detect by the pat... View full abstract»

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  • Fast algorithm for modular reduction

    Publication Year: 1998, Page(s):265 - 271
    Cited by:  Papers (14)  |  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (636 KB)

    The paper presents an algorithm for computing the residue R=X mod M. The algorithm is based on a sign estimation technique that estimates the sign of a number represented by a carry-sum pair produced by a carry save adder. Given the (n+k)-bit X and the n-bit M, the modular reduction algorithm computes the n-bit residue R in O(k+log n) time, and is particularly useful when the operand size is large... View full abstract»

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  • Modular multiplication method

    Publication Year: 1998, Page(s):317 - 318
    Cited by:  Papers (2)  |  Patents (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (160 KB)

    The Montgomery algorithm has been widely used in modern cryptography because it is effective for modular exponentiation. However, it is not efficient when used for just a few modular multiplications. Inefficiency is due to the large overhead involved in the residue transformation of arguments. A new modular multiplication method using the Montgomery reduction algorithm is presented which can elimi... View full abstract»

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  • Hardware-efficient systolic architecture for inversion and division in GF(2m)

    Publication Year: 1998, Page(s):272 - 278
    Cited by:  Papers (19)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (576 KB)

    Two parallel-in parallel-out systolic arrays for computing inverses and divisions in finite fields GF(2m) with the standard basis representation are presented. Both architectures realise a new variant of Euclid's algorithm. One of the proposed arrays involves O(m2) area complexity and O(1) time complexity, while the other involves O(m) area complexity and O(m) time complexity... View full abstract»

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  • Analysis of radix searching of exponential bidirectional associative memory

    Publication Year: 1998, Page(s):279 - 285
    Cited by:  Papers (3)  |  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (556 KB)

    The exponential bidirectional associative memory (eBAM) is a high-capacity associative memory. However, in the hardware realisation of eBAM, increasing efforts have been made to obtain an optimally small radix of exponential circuit for the fixed dynamic range of the VLSI circuit transistor, thereby allowing the dimension of the stored patterns to reach maximum. In this paper, the authors prove th... View full abstract»

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