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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • Date May 1998

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Displaying Results 1 - 10 of 10
  • On crossing minimization problem

    Publication Year: 1998, Page(s):406 - 418
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    In this paper, we consider a problem related to global routing postoptimization: the crossing minimization problem (CMP). Given a global routing representation, the CMP is to minimize redundant crossings between every pair of nets. In particular, there are two kinds of CMP: constrained CMP (CCMP) and unconstrained CMP (UCMP). These problems have been studied previously where an O(m2n) a... View full abstract»

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  • Multicycle generalization. A new way to improve the convergence of waveform relaxation for circuit simulation

    Publication Year: 1998, Page(s):435 - 443
    Cited by:  Papers (1)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (196 KB)

    In the present work, we describe a new algorithm, capable of considerably improving the convergence of waveform relaxation, that is based on a special multicycle or nested organization of the iteration process. Mathematically, it can be classified as a polynomially accelerated method applicable to systems containing “black boxes.” The convergence area is shown to be wider for a larger ... View full abstract»

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  • LOT: Logic Optimization with Testability. New transformations for logic synthesis

    Publication Year: 1998, Page(s):386 - 399
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed-Muller expansions have been introduced in the synthesis of multilevel circ... View full abstract»

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  • The complexity of the inclusion operation on OFDD's

    Publication Year: 1998, Page(s):457 - 459
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (80 KB)

    Ordered functional decision diagrams (OFDD's) are a data structure for representation and manipulation of Boolean functions. A polynomial time algorithm for the test whether f⩽g for functions f and g given by OFDD's is presented. This is the last basic operation on OFDD's whose complexity was unknown. The result also solves an open question on the complexity of minimizing OFDD's for incomplete... View full abstract»

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  • Model-adaptable MOSFET parameter-extraction method using an intermediate model

    Publication Year: 1998, Page(s):400 - 405
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    We present a parameter-extraction method that is applicable to many metal-oxide-semiconductor field-effect-transistor (MOSFET) models. A simple intermediate model is introduced to eliminate model dependency of parameter estimation for numerical optimization techniques. The process of the parameter estimation is decomposed into two parts: extraction of parameters of the intermediate model and trans... View full abstract»

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  • Performance optimization by gate sizing and path sensitization

    Publication Year: 1998, Page(s):459 - 462
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (128 KB)

    In the circuit model where outputs are latched and input vectors are successively applied at inputs, the gate resizing approach to reduce the delay of the critical path may not improve the performance. Since the clock period is determined by delays of both long and short paths in the combinational circuit, gates lying in sensitizable long and short paths can be selected for resizing. For feasible ... View full abstract»

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  • A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic

    Publication Year: 1998, Page(s):419 - 434
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    This paper presents the first reported joint gate sizing and buffer insertion method for minimizing the delay of power constrained combinational logic networks that can incorporate a mixture of unbuffered and buffered gates (or mixture of CMOS and BiCMOS gates). In the method, buffered gates in a network are decided on by an iterative process that uses a sequence of sizing optimizations where afte... View full abstract»

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  • Address generation for memories containing multiple arrays

    Publication Year: 1998, Page(s):377 - 385
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (312 KB)

    We present techniques for generating addresses for memories containing multiple arrays. Because these techniques rely on the inversion or rearrangement of address bits, they are faster and require less hardware to compute than the traditional technique of addition. Use of these techniques can improve performance and cost of application-specific memory subsystems by decreasing effective access time... View full abstract»

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  • Zero-aliasing space compaction using linear compactors with bounded overhead

    Publication Year: 1998, Page(s):452 - 457
    Cited by:  Papers (37)  |  Patents (31)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    Space compaction is employed in built-in self-testing schemes to compress the test responses from a k-output circuit to q signature streams, where q≪k. The effectiveness of a compaction method is measured by its compaction ratio k/q and the amount of hardware required to implement the compaction circuit. However, a high compaction ratio can require a very large compactor as well as introduce al... View full abstract»

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  • Rebel: a clustering algorithm for look-up table FPGA's

    Publication Year: 1998, Page(s):444 - 451
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (216 KB)

    Rebel is a new algorithm for clustering gates into k-input function blocks for look-up table field-programmable gate arrays (FPGA's). The algorithm propagates functional dependencies forward through a logic network, combining gates into clusters according to a heuristic metric. Rebel does a good job of handling reconvergent circuits, duplicating logic when it makes sense to do so, in addition, Reb... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu