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# IEE Proceedings - Circuits, Devices and Systems

## Filter Results

Displaying Results 1 - 13 of 13
• ### Synthesis of MVL functions using input and output assignments

Publication Year: 1998, Page(s):207 - 212
Cited by:  Papers (1)
| | PDF (444 KB)

A number of decomposition based mapping techniques are proposed. In these techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimisation is obtained by constructing matching-count matrix'. The entries of the matching-count matrix MCij represent the number of entry matches between the input variable number i in the input matrix (X... View full abstract»

• ### Integrated universal biquad based on triple-output OTAs and using digitally programmable zeros

Publication Year: 1998, Page(s):192 - 196
Cited by:  Papers (8)  |  Patents (1)
| | PDF (500 KB)

The authors describe how triple-output OTAs facilitate the development of a new current-mode universal biquad configuration capable of generating various filter transfer functions using digitally programmable zeros. This is achieved without excessive use of active devices and without changing the biquad topology. The biquad zeros may be independently programmed using four switches producing the fo... View full abstract»

• ### Realisation of soft morphological filters

Publication Year: 1998, Page(s):201 - 206
Cited by:  Papers (1)
| | PDF (436 KB)

A new technique for the realisation of soft morphological filters based on the majority gate algorithm is presented. A pipelined systolic array architecture suitable to perform soft morphological filtering is also presented. The processing times of the proposed hardware structure do not depend on the data window size and the required silicon area is linearly related to the number of its inputs and... View full abstract»

• ### Turn-off analysis of PT and NPT IGBTs in zero-current switching

Publication Year: 1998, Page(s):185 - 191
| | PDF (496 KB)

The lower turn-off losses in zero-current switching (ZCS) converters as compared to the conventional hard switching mode using insulated gate bipolar transistors (IGBT), depends on the intrinsic bipolar junction transistor structure. Whichever the IGBT type may be, a significant part of the stored charge is removed from the base of the intrinsic bipolar junction transistor in ZCS because of the sp... View full abstract»

• ### Inductance in VLSI interconnection modelling

Publication Year: 1998, Page(s):175 - 179
Cited by:  Papers (14)
| | PDF (632 KB)

The present trend of increasing speed of operation in integrated circuits may produce transmission line effects in the interconnections. To decide whether these effects are important and should be taken into account in the interconnection modelling, an evaluation of characteristic impedance and signal time propagation is needed. These two parameters are calculated from capacitance and inductance v... View full abstract»

• ### Novel low-cost, low-power modulator/demodulator using a single GaAs field effect transistor

Publication Year: 1998, Page(s):165 - 169
Cited by:  Papers (1)
| | PDF (480 KB)

A novel type of transponder circuit for localisation and identification purposes is presented. The complete circuit contains only one semiconductor device, a cold' field effect transistor, which performs both the modulator and the demodulator functions. This makes possible the realisation of a low-cost, low-power, high-performance 10 GHz transponder in miniature format. The design of the circuit ... View full abstract»

• ### Optimised weighted-resistor digital to analogue converter

Publication Year: 1998, Page(s):197 - 200
Cited by:  Papers (2)
| | PDF (232 KB)

From the classical weighted-resistor (WR) digital to analogue converter (DAC), two-stage DACs are derived. Conditions for minimum spread and the minimum total resistance for the two-stage DACs are derived. The theory is extended to multistage WR DACs. Thus, an optimised WR DAC is obtained that has minimum spread and the minimum total resistance and is therefore, suitable for economic fabrication i... View full abstract»

• ### Efficient real-time modelling of substrate coupling in large mixed-signal Spice designs, using analogue HDL

Publication Year: 1998, Page(s):180 - 184
Cited by:  Papers (2)  |  Patents (4)
| | PDF (428 KB)

In large mixed-signal circuits, digitally-injected substrate noise has recently been recognised as a key problem for circuit designers. However, no published procedure exists which allows circuit designers to efficiently model the substrate noise and coupling to the analogue circuitry in large mixed-signal Spice designs. Such a methodology is presented and is extended to employ novel analogue HDL ... View full abstract»

• ### Novel velocity-electric field relation for modelling of compound semiconductor field-effect transistors

Publication Year: 1998, Page(s):170 - 174
| | PDF (400 KB)

A novel empirical relation is proposed for the velocity-electric-field profile of compound semiconductors. The velocity-field curve in compound semiconductors (e.g. GaAs, InP etc.) has a peak which is followed by a negative-differential-resistance region in which the velocity decreases continuously with increase in the electric field. The proposed empirical fit is a two-piece nonlinear approximati... View full abstract»

• ### Hardware implementation of a pulse-stream neural network

Publication Year: 1998, Page(s):141 - 147
Cited by:  Papers (5)
| | PDF (640 KB)

The authors describe the design and test of an artificial neural network, using a pulse-stream approach, that is implemented using BiCMOS technology. Networks are constructed from arrays of customised neuron chips and synapse chips. The neuron chip uses novel circuitry to implement an accurate sigmoid transfer characteristic. The synapse chip uses a new pulse-stream implementation of the different... View full abstract»

• ### Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

Publication Year: 1998, Page(s):148 - 154
Cited by:  Papers (6)
| | PDF (912 KB)

The design and analysis of a ±1 V CMOS four-quadrant analogue multiplier and a frequency doubler for low-voltage low-power applications are presented. The design is based on the current-mode approach and the square-law characteristics of an MOS transistor in saturation. The multiplier utilises I-V converters, a current mirror and four matched transistors to achieve a transresistance gain of... View full abstract»

• ### Built-in self-test generator design using nonuniform cellular automata model

Publication Year: 1998, Page(s):155 - 161
Cited by:  Papers (2)  |  Patents (4)
| | PDF (676 KB)

The paper presents a new test vector generator construction technique for built-in self-test (BIST). The technique is based on the cellular automata model nonuniform cellular automata (NUCA). In NUCA, cell neighbourhoods are not predefined but decided for each cell dynamically by the test vector set. The problem of finding the minimum NUCA topology that can generate a given precomputed test vector... View full abstract»

• ### GaAs MOSFET using MBE-grown Ga2O3 (Gd2 O3) as gate oxide

Publication Year: 1998, Page(s):162 - 164
Cited by:  Papers (1)  |  Patents (1)
| | PDF (268 KB)

An enhancement mode GaAs metal-oxide-semiconductor field effect transistor (MOSFET) with Ga2O3 (Gd2O 3) as gate dielectric has been successfully fabricated. The low interface density Ga2O3 (Gd2O3 ) oxide and GaAs n-channel layer were grown by in situ molecular beam epitaxy (MBE). The fabricated n-channel MOSFET... View full abstract»