Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Circuits, Devices and Systems, IEE Proceedings -

Issue 3 • Date Jun 1998

Filter Results

Displaying Results 1 - 13 of 13
  • Inductance in VLSI interconnection modelling

    Publication Year: 1998 , Page(s): 175 - 179
    Cited by:  Papers (11)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (632 KB)  

    The present trend of increasing speed of operation in integrated circuits may produce transmission line effects in the interconnections. To decide whether these effects are important and should be taken into account in the interconnection modelling, an evaluation of characteristic impedance and signal time propagation is needed. These two parameters are calculated from capacitance and inductance values obtained by simulation using an industrial software tool. Typical VLSI interconnection dimensions are considered, studying the influence of design variables (distance between lines and length) on the values obtained. The relative magnitude of these parameters has an effect on which interconnect model best suits a certain interconnection. Ranges of validity of the different models are given for typical cases View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Turn-off analysis of PT and NPT IGBTs in zero-current switching

    Publication Year: 1998 , Page(s): 185 - 191
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (496 KB)  

    The lower turn-off losses in zero-current switching (ZCS) converters as compared to the conventional hard switching mode using insulated gate bipolar transistors (IGBT), depends on the intrinsic bipolar junction transistor structure. Whichever the IGBT type may be, a significant part of the stored charge is removed from the base of the intrinsic bipolar junction transistor in ZCS because of the spontaneous current decrease, and because of the antiparallel diode turn-on. The turn-off loss reduction is especially significant when the carrier lifetime is low View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimised weighted-resistor digital to analogue converter

    Publication Year: 1998 , Page(s): 197 - 200
    Cited by:  Papers (2)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (232 KB)  

    From the classical weighted-resistor (WR) digital to analogue converter (DAC), two-stage DACs are derived. Conditions for minimum spread and the minimum total resistance for the two-stage DACs are derived. The theory is extended to multistage WR DACs. Thus, an optimised WR DAC is obtained that has minimum spread and the minimum total resistance and is therefore, suitable for economic fabrication in integrated circuit form View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel low-cost, low-power modulator/demodulator using a single GaAs field effect transistor

    Publication Year: 1998 , Page(s): 165 - 169
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (480 KB)  

    A novel type of transponder circuit for localisation and identification purposes is presented. The complete circuit contains only one semiconductor device, a `cold' field effect transistor, which performs both the modulator and the demodulator functions. This makes possible the realisation of a low-cost, low-power, high-performance 10 GHz transponder in miniature format. The design of the circuit makes use of simple and reliable methods for the modulator function. The demodulator is a FET detector, which exploits the nonlinear channel resistance of the transistor instead of the Schottky barrier. A theory of this type of detector is given View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in self-test generator design using nonuniform cellular automata model

    Publication Year: 1998 , Page(s): 155 - 161
    Cited by:  Papers (2)  |  Patents (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    The paper presents a new test vector generator construction technique for built-in self-test (BIST). The technique is based on the cellular automata model nonuniform cellular automata (NUCA). In NUCA, cell neighbourhoods are not predefined but decided for each cell dynamically by the test vector set. The problem of finding the minimum NUCA topology that can generate a given precomputed test vector sequence is worked on and reduced to independent set-covering problems. Also, a polynomial time algorithm that decides on a small, but not minimal, cellular topology is introduced. Simulations using benchmark circuits showed that the hardware component cost of a test vector generator based on the NUCA model is considerably less than the cost of a single programmable logic array (PLA) approach View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hardware implementation of a pulse-stream neural network

    Publication Year: 1998 , Page(s): 141 - 147
    Cited by:  Papers (4)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (640 KB)  

    The authors describe the design and test of an artificial neural network, using a pulse-stream approach, that is implemented using BiCMOS technology. Networks are constructed from arrays of customised neuron chips and synapse chips. The neuron chip uses novel circuitry to implement an accurate sigmoid transfer characteristic. The synapse chip uses a new pulse-stream implementation of the differential amplifier and requires only five transistors to produce a linear multiplier. Measured results from the chips show that the neuron has an accurate sigmoid transfer characteristic and gradient suitable for the error backpropagation learning algorithm. The synapse has excellent 1% linearity and properties suitable for multiplication. The chips have been used to implement a three-layer artificial neural network which has been tested using hard learning problems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Synthesis of MVL functions using input and output assignments

    Publication Year: 1998 , Page(s): 207 - 212
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (444 KB)  

    A number of decomposition based mapping techniques are proposed. In these techniques, the synthesis problem is formulated as a mapping from an input matrix to an output matrix. The minimisation is obtained by constructing `matching-count matrix'. The entries of the matching-count matrix MCij represent the number of entry matches between the input variable number i in the input matrix (X) and the output function number j in the output matrix (Y). It then selects those input output pairings that give the maximum matching count, thus maximising the number of switching operations which can be eliminated in the realisation of multiple-valued logic (MVL) functions. The proposed techniques are classified as: output-phase with complement, input-phase with and without complement. Numerical results are presented to show that the proposed techniques result in significant reduction in the number of switching operators required for the implementation of 5000 randomly generated r-valued functions (for r=3, 4 and 5). It is also shown that the input-phase assignment techniques do not require any additional hardware circuitry at the output to restore the original function. This may give this technique an edge over other techniques View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Realisation of soft morphological filters

    Publication Year: 1998 , Page(s): 201 - 206
    Cited by:  Papers (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    A new technique for the realisation of soft morphological filters based on the majority gate algorithm is presented. A pipelined systolic array architecture suitable to perform soft morphological filtering is also presented. The processing times of the proposed hardware structure do not depend on the data window size and the required silicon area is linearly related to the number of its inputs and the image resolution View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated universal biquad based on triple-output OTAs and using digitally programmable zeros

    Publication Year: 1998 , Page(s): 192 - 196
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    The authors describe how triple-output OTAs facilitate the development of a new current-mode universal biquad configuration capable of generating various filter transfer functions using digitally programmable zeros. This is achieved without excessive use of active devices and without changing the biquad topology. The biquad zeros may be independently programmed using four switches producing the following filtering functions: lowpass, highpass, bandpass, notch, allpass and lowpass notch. Further advantages of the biquad are (ω0 and Q) electronic tunability, low sensitivity and ease of design. Fabricated in a 0.8 μm double-metal, double-poly CMOS process, the universal biquad occupies an active chip area of 0.6 mm2. For demonstration purposes, simulated and measured results of voltage tunable lowpass and bandpass filters over the frequency range of 0.7 MHz to 4 MHz are included View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Novel velocity-electric field relation for modelling of compound semiconductor field-effect transistors

    Publication Year: 1998 , Page(s): 170 - 174
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    A novel empirical relation is proposed for the velocity-electric-field profile of compound semiconductors. The velocity-field curve in compound semiconductors (e.g. GaAs, InP etc.) has a peak which is followed by a negative-differential-resistance region in which the velocity decreases continuously with increase in the electric field. The proposed empirical fit is a two-piece nonlinear approximation, the first part being a third-order polynomial and the second part being an exponential relation to ensure the continuity and smoothness over the entire region. The accuracy of the model is confirmed by comparing and contrasting the proposed empirical curve with the available experimental and simulated results. The proposed model is expected to find useful application in analytical modelling of field-effect transistors View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient real-time modelling of substrate coupling in large mixed-signal Spice designs, using analogue HDL

    Publication Year: 1998 , Page(s): 180 - 184
    Cited by:  Papers (1)  |  Patents (3)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (428 KB)  

    In large mixed-signal circuits, digitally-injected substrate noise has recently been recognised as a key problem for circuit designers. However, no published procedure exists which allows circuit designers to efficiently model the substrate noise and coupling to the analogue circuitry in large mixed-signal Spice designs. Such a methodology is presented and is extended to employ novel analogue HDL (hardware description language) models, providing real-time capability. The efficiency and practicality of the proposed methodology are demonstrated in two example circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • GaAs MOSFET using MBE-grown Ga2O3 (Gd2 O3) as gate oxide

    Publication Year: 1998 , Page(s): 162 - 164
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (268 KB)  

    An enhancement mode GaAs metal-oxide-semiconductor field effect transistor (MOSFET) with Ga2O3 (Gd2O 3) as gate dielectric has been successfully fabricated. The low interface density Ga2O3 (Gd2O3 ) oxide and GaAs n-channel layer were grown by in situ molecular beam epitaxy (MBE). The fabricated n-channel MOSFET with 20 nm-thick oxide and 2 μm-long gate operated both in enhancement and depletion modes, with a peak transconductance of 40 mS/mm in the enhancement mode. While operating with gate voltages ranging from -1 to 5 V, the device showed a drain current drift of 10.5% for a duration of 104s, a limited amount of hysteresis and negligible dispersion of transconductance from 10 Hz to 1 MHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and analysis of a ±1 V CMOS four-quadrant analogue multiplier

    Publication Year: 1998 , Page(s): 148 - 154
    Cited by:  Papers (5)
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (912 KB)  

    The design and analysis of a ±1 V CMOS four-quadrant analogue multiplier and a frequency doubler for low-voltage low-power applications are presented. The design is based on the current-mode approach and the square-law characteristics of an MOS transistor in saturation. The multiplier utilises I-V converters, a current mirror and four matched transistors to achieve a transresistance gain of 73 dBΩ, a -3 dB bandwidth of 4.3 MHz, a total harmonic distortion below 1% and a maximum power dissipation of 130 μW. Design guidelines have been set to link the circuit performance, in terms of the gain, the input operating range, the fabrication area, and the device aspect ratios, to key device and technology parameters. The scope for further performance improvement using BiCMOS is also highlighted. The experimental results obtained from the chip were found to be in close agreement with the simulated results View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.