Issue 7 • Date July 1998
Filter Results
Displaying Results 1 - 25 of 27
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The 23rd European Solid-state Circuits Conference
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PDF (18 KB)
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Guest Editorial
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PDF (24 KB)
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R, G, B acquisition interface with line-locked clock generator for flat panel display
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PDF (180 KB)
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Embedded 5 V-to-3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology
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PDF (248 KB)
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A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F2 cell [CMOS design]
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PDF (224 KB)
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A compact low-power BiCMOS log-domain filter
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PDF (200 KB)
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A 3.3-V, low-distortion ISDN line driver with a novel quiescent current control circuit
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PDF (108 KB)
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A robust CMOS compander
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PDF (160 KB)
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Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic
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PDF (176 KB)
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Aims & Scope
The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.
Meet Our Editors
Editor-in-Chief
Un-Ku Moon
Oregon State University, EECS


