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Solid-State Circuits, IEEE Journal of

Issue 1 • Date Feb. 1988

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Displaying Results 1 - 25 of 45
  • Perspective on BiCMOS VLSIs

    Publication Year: 1988 , Page(s): 5 - 11
    Cited by:  Papers (41)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (767 KB)  

    A high-performance BiCMOS technology (Hi-BiCMOS) and its applications to VLSIs are described. By combining bipolar and CMOS devices in unit circuits of VLSIs, Hi-BiCMOS provides both speed performance competitive with bipolar LSIs and integration density close to that of CMOS LSIs. Hi-BiCMOS technology has been successfully used for static RAMs, dynamic RAMs, and gate arrays. The effectiveness of its applications to some types of processors has also been examined by evaluating test chips.<> View full abstract»

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  • A 30- mu A data-retention pseudostatic RAM with virtually static RAM mode

    Publication Year: 1988 , Page(s): 12 - 19
    Cited by:  Papers (4)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (950 KB)  

    A 1-Mb (128K*8) pseudostatic RAM (PSRAM) is described. A novel feature of the RAM is the inclusion of a virtually static RAM (VSRAM) mode, while being fully compatible with a standard PSRAM. The RAM changes into the VSRAM mode when the RFSH pin is grounded, even in active cycles. The RAM can be used either as a fast PSRAM of 36-ns access time or as a convenient VSRAM of 66-ns access time. The typical operation current and data-retention current are 30 mA at 160-ns cycle time and 30 mu A, respectively. In order to achieve high-speed operation, low data-retention current, and high reliability, the RAM uses delay-time tunable design, a current-mirror timer, hot-carrier resistant circuits, and an optimized arbiter. These technologies are applicable to general advanced VLSIs.<> View full abstract»

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  • A 4-Mbit DRAM with 16-bit concurrent ECC

    Publication Year: 1988 , Page(s): 20 - 26
    Cited by:  Papers (17)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    A 256 K-word*16-bit dynamic RAM with concurrent 16-bit error correction code (ECC) has been built in 0.8- mu m CMOS technology, with double-level metal and surrounding high-capacitance cell. The cell measures 10.12 mu m/sup 2/ with a 90-fF storage capacitance. A duplex bit-line architecture used on the DRAM provides multiple-bit operations and the potential of high-speed data processing for ASIC memories. The ECC checks concurrently 16-bit data and corrects a 1-bit data error. This ECC method can be adapted to higher-bit ECC without expanding the memory array. The ratio of ECC area to the whole chip is 7.5%. The cell structure and the architecture allow for expansion to 16-Mb DRAM. The 4-Mb DRAM has a 70-ns RAS access time without ECC and a 90-ns RAS access time with ECC.<> View full abstract»

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  • An experimental large-capacity semiconductor file memory using 16-levels/cell storage

    Publication Year: 1988 , Page(s): 27 - 33
    Cited by:  Papers (26)  |  Patents (67)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (687 KB)  

    A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3- mu m CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 mu s, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10/sup -7/ h/sup -1/).<> View full abstract»

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  • High-speed sensing scheme for CMOS DRAMs

    Publication Year: 1988 , Page(s): 34 - 40
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB)  

    A significant improvement in sensing speed over the half-V/sub DD/ bit-line precharge sensing scheme is obtained by precharging the bit line to approximately 2/3 V/sub DD/. The 2/3-V/sub DD/ sensing scheme also results in higher-bit-line capacitance, asymmetrical bit-line swing, and higher power consumption. However, the speed advantage of 2/3-V/sub DD/ sensing may outweigh the disadvantages and can significantly improve DRAM performance. For the unboosted word-line case, symmetrical bit-line swing can be retained by limiting the bit-line downward voltage swing through a clamping circuit added to the sense amplifier, resulting in almost no loss of stored charge in a cell. The authors show that the 2/3-V/sub DD/ sensing with a limited bit-line swing has several distinct advantages over the half-V/sub DD/ sensing scheme and is particularly suitable for high-performance high density CMOS DRAMs.<> View full abstract»

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  • Offset word-line architecture for scaling DRAMs to the gigabit level

    Publication Year: 1988 , Page(s): 41 - 47
    Cited by:  Papers (2)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (674 KB)  

    An alternative to the boosted word-line DRAM architecture is described that is scalable to the gigabit level and avoids the problems of poor performance and high gate fields of conventional boosted word-line circuits. The alternative is called an offset word-line architecture, because the cell switch is changed to depletion mode and the word line is pulled beyond the cell switch device's source voltage rather than boosted beyond its drain voltage. The large voltage swing for the word line does not cause large fields across the gate dielectric in the word-line driver or array access device because the gates of some devices use materials with modified work functions. The word-line voltage swing can be greater than the bit-line voltage swing plus the required threshold voltage even for gigabit-scale integration DRAM technologies.<> View full abstract»

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  • Voltage limiters for DRAMs with substrate-plate-electrode memory cells

    Publication Year: 1988 , Page(s): 48 - 52
    Cited by:  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (463 KB)  

    To prevent substrate-plate-electrode (SPE) cell weakness due to substrate-bias voltage bounce, voltage limiters were applied to both the substrate and the sense-circuit supply source. A supply voltage V/sub CC/ bump test was introduced to evaluate their effectiveness. The voltage limiters have been implemented on an experimental 4-Mb DRAM. It was found that a wider operational margin, as compared to conventional DRAMs (without voltage limiters) having SPE cells, was achievable through the use of voltage limiters. These voltage limiters may be considered suitable for wide operational margin DRAMs with SPE cells. The substrate-bias voltage limiter, in particular, is more effective than the sense-circuit supply voltage limiter and offers a means of improving the operational margin of V/sub CC/ bump.<> View full abstract»

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  • A 46-ns 1-Mbit CMOS SRAM

    Publication Year: 1988 , Page(s): 53 - 58
    Cited by:  Papers (5)  |  Patents (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (570 KB)  

    A 1-Mb (128 K*8-bit) CMOS static RAM (SRAM) with high-resistivity load cell has been developed with 0.8- mu m CMOS process technology. Standby power is 25 mu W, active power 80 mW at 1-MHz WRITE operation, and access time 46 ns. The SRAM uses a PMOS bit-line DC load to reduce power dissipation in the WRITE cycle, and has a four-block access mode to reduce the testing time. A small 4.8*8.5- mu m/sup 2/ cell has been realized by triple-polysilicon layers. The grounded second polysilicon layer increases cell capacitance and suppresses alpha -particle-induced soft errors. The chip size is 7.6*12.4 mm/sup 2/.<> View full abstract»

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  • Fast CMOS ECL receivers with 100-mV worst-case sensitivity

    Publication Year: 1988 , Page(s): 59 - 67
    Cited by:  Papers (35)  |  Patents (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1026 KB)  

    CMOS emitter-coupled logic (ECL) receiver circuits consisting of a differential-amplifier stage and a CMOS inverter are shown to convert 100-mV input signals to on-chip CMOS levels even with worst-case parameter variations in a 5-V 1- mu m technology. Two different receiver circuits are used to cover a range of power supply options; a third circuit provides a comparison case. The differential amplifiers feature built-in feedback compensation for common-mode parameter variations. The differential input devices are designed with large widths, minimum channel lengths, and an interleaved layout to enhance gain, speed, and margin for differential mismatches. The simplicity of the circuits and the effectiveness of the built-in compensation facilitate analysis. Partitioning and simplifying assumptions are used to thoroughly test the worst case without complex simulations, while providing insight into the design process.<> View full abstract»

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  • BiCMOS circuit technology for a high-speed SRAM

    Publication Year: 1988 , Page(s): 68 - 73
    Cited by:  Papers (16)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (505 KB)  

    BiCMOS circuit technology for a high-speed and large-capacity ECL-compatible static RAM (SRAM) is described. To obtain high-speed and low-power operation, a decoder with a pre-main decode configuration having an ECL-interface circuit and a word driver with BiCMOS inverter are proposed. A BiCMOS multiplexer with a single emitter-follower driver is also proposed. An optimization method for memory cell array configuration is presented that minimizes the total delay time and the total power dissipation of SRAMs. Circuit simulation results show that a 64-kbit ECL-compatible SRAM with an access time of less than 7 ns and a power dissipation of less than 1 W is obtainable.<> View full abstract»

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  • Content-addressable memory for VLSI pattern inspection

    Publication Year: 1988 , Page(s): 74 - 78
    Cited by:  Papers (5)  |  Patents (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (591 KB)  

    In the template-set approach to VLSI pattern inspection, all patterns in a local window (i.e. a 5*5 array of pixels) that are allowed by the design rules are collected as a template set, and an image in the window centered at each pixel position is compared to the templates to determine whether the pattern is defective. To make this method practical, the number of acceptable templates must be reasonably small and template matching must be fast. By introducing don't-care conditions into the templates, the number of required templates was reduced. A maskable content-addressable memory was used to implement templates with don't-care conditions and to permit parallel comparison of an incoming pattern with all templates in the set. A custom VLSI chip was designed with a 2- mu m double-metal CMOS technology, which can perform parallel template matching at the rate of 1.6*10/sup 7/ local images per second.<> View full abstract»

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  • A 50-ns 256 K CMOS split-gate EPROM

    Publication Year: 1988 , Page(s): 79 - 85
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (699 KB)  

    A high-speed 32 K*8 CMOS EPROM has been designed and implemented in a polycide 1.2- mu m n-well epi CMOS technology. A high-read-current split-gate EPROM cell combined with address transition detection-based SRAM-like precharge, equalization, and clocked differential sensing schemes has resulted in a typical address access time of less than 50 ns. The typical power dissipation at 18.2 MHz is 60 mW. Row redundancy is used to enhance the yield and the part has been designed to be compatible with plastic packaging.<> View full abstract»

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  • A new architecture for the NVRAM-an EEPROM backed-up dynamic RAM

    Publication Year: 1988 , Page(s): 86 - 90
    Cited by:  Papers (5)  |  Patents (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (604 KB)  

    An architecture for a nonvolatile RAM (NVRAM) suitable for high-density applications is described. In the cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is constructed between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM and the EEPROM. The process of the NVRAM is compatible with ordinary EEPROMs.<> View full abstract»

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  • Complementary current-mirror logic

    Publication Year: 1988 , Page(s): 91 - 97
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (677 KB)  

    A logic family which operates primarily on current rather than voltage levels is proposed. This family can perform with the high speed of emitter-coupled logic (ECL), and so is a suitable candidate for mainframe computer use. In addition, the inherent gate power dissipation in the absence of an input signal resembles CMOS, making large-scale integration a possibility. Simulated results using 12-GHz n-p-n and 1.2-GHz p-n-p devices show that 120-ps gate delay is possible at a 1-mW power level. The performance of a basic logic cell and ways of forming several types of logic circuits are discussed. Line-driving capability is compared with ECL, and in many situations it is found to compare very favorably in terms of energy requirements as well as line-to-line noise coupling. The potential for multilevel applications is briefly discussed.<> View full abstract»

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  • A high-speed shuffle bus for VLSI arrays

    Publication Year: 1988 , Page(s): 98 - 104
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (648 KB)  

    A high-speed shuffle bus which is able to implement various kinds of communication schemes for VLSI processor arrays is presented. Because of the simple and modular nature of the shuffle bus, the processor arrays can now be easily modularized and equipped with flexible capabilities for both global and neighboring communications. With data swapping at a rate as high as 200 MHz between adjacent registers, the shuffle bus is about 20 times faster than those bidirectional pipelined buses. The shuffle bus may be expanded to accommodate any number of nodes with an arbitrary number of bits in each word. With only a few sets of control patterns, the shuffle bus can be applied to the implementation of a wide variety of interconnection networks, sorting networks, FIFO, and associative memory.<> View full abstract»

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  • A memory-based high-speed digital delay line with a large adjustable length

    Publication Year: 1988 , Page(s): 105 - 110
    Cited by:  Papers (9)  |  Patents (28)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (438 KB)  

    The digital delay line concept is based on a dynamic three-transistor cell memory, with pointer access and offers high operating frequency, large maximum length, and low power dissipation. The adjustable delay requires only a small overhead for control logic. An experimental chip with 60 K transistors, which utilizes this concept, has been built in a 1.5- mu m CMOS technology. The adjustable delay ranges from 1 to 4096 clock cycles for a 4-bit-wide data word. Correct operation of the chip has been verified for clock frequencies in the range of 3 kHz to 30 MHz. Therefore the circuit is suitable for audio as well as video applications.<> View full abstract»

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  • An elastic pipeline mechanism by self-timed circuits

    Publication Year: 1988 , Page(s): 111 - 117
    Cited by:  Papers (15)  |  Patents (70)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (855 KB)  

    An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors.<> View full abstract»

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  • A DSP line equalizer VLSI for TCM digital subscriber-line transmission

    Publication Year: 1988 , Page(s): 118 - 123
    Cited by:  Papers (2)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (656 KB)  

    The architecture of a line equalizer using digital-signal-processing (DSP) techniques is described. The equalizer is utilized in 320-kb/s time-compression multiplexing (TCM) subscriber-line transmission systems in the integrated services digital network (ISDN). It consists of two digital filter blocks, called the square root f equalizer and the bridged-tap equalizer, and gain- and timing-control blocks. The square root f equalizer achieves the processing speed of 20 MOPS by a powerful arithmetic unit composed of multipliers and adders. It provides an FIR filter with nine taps which satisfies an accurate equalization for the 1.92-Msample/s data. The bridged-tap equalizer performs both the adaptation algorithm of the square root f equalizer and the decision-feedback algorithm. The microprogram control enables the hardware to be shared between these functions and assures flexibility. Algorithm-oriented instructions implemented in the ALU realize high-speed execution of the decision-feedback algorithm with a simple architecture. The 11.3-mm*8.5-mm chip with 61 K transistors has been implemented using 1.5- mu m double-metal-layer CMOS technology.<> View full abstract»

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  • A 32*32-bit multiplier using multiple-valued MOS current-mode circuits

    Publication Year: 1988 , Page(s): 124 - 132
    Cited by:  Papers (49)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (884 KB)  

    A 32*32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2- mu m CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32*32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2*5.2 mm/sup 2/, which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported.<> View full abstract»

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  • An 8-bit 2-ns monolithic DAC

    Publication Year: 1988 , Page(s): 142 - 146
    Cited by:  Papers (6)  |  Patents (25)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (533 KB)  

    An 8-bit resolution ultrahigh-speed monolithic digital-to-analog converter (DAC) is fabricated using super self-aligned process technology. In order to improve dynamic accuracy, which is determined by settling speed, clock feedthrough noise, and glitch, a number of circuit technologies are developed including a rise- and fall-time control switch driver, a low-noise flip-flop, and a differential buffer configuration. In addition, a chip assembly technology using a multilayer ceramic substrate is developed. The DAC exhibits a settling time to 8-bit accuracy of about 2 ns, a maximum conversion rate of 1 GHz, a glitch energy of 2 ps-V, and a 10-bit linearity error accuracy without trimming.<> View full abstract»

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  • A 400-MHz DA converter with a 4-bit color map for 2000-line display

    Publication Year: 1988 , Page(s): 147 - 151
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (518 KB)  

    A video digital-to-analog (DA) converter with a color map is discussed that is monolithic, bipolar, and achieves ultrahigh speed. When the chip is addressed with 4-bit video data, 256-step color-map data can be used in an extremely high-definition 2000-pixel*2000-pixel display. A combination of two emitter-coupled logic (ECL) RAMs and a data-multiplex DA converter is used. The conversion rate is 400 MHz, the settling time of the DA converter is 2 ns, the rise and fall times are both 0.8 ns, and the power consumption is 1.3 W.<> View full abstract»

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  • A cyclic A/D converter that does not require ratio-matched components

    Publication Year: 1988 , Page(s): 152 - 158
    Cited by:  Papers (32)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (735 KB)  

    The circuit configuration of a cyclic analog-to-digital (A/D) converter using switched-capacitor techniques is described. The analog portion of the circuit consists of two operational amplifiers, four capacitors, and ten switches regardless of the number of bits per sample converted, and completes an n-bit conversion in 3n clock cycles. The conversion characteristics are inherently insensitive both to capacitor ratio and to amplifier offset voltage. The circuit, therefore, can be realized in a small die area. The effects of finite amplifier gain and switch charge injection on the conversion accuracy are discussed. A prototype chip has been fabricated in a 2- mu m CMOS technology operating on a single 5-V supply. When it is operated as an 8-bit converter at a sampling rate of 8 kHz, the maximum conversion error is 0.2 LSB (least-significant bit) for differential nonlinearity and 0.5 LSB for integral nonlinearity. The die area measures 0.79 mm/sup 2/.<> View full abstract»

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  • A high-speed CMOS comparator for use in an ADC

    Publication Year: 1988 , Page(s): 159 - 165
    Cited by:  Papers (33)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (635 KB)  

    A dynamic latch preceded by an offset-cancelled amplifier is used in the 3- mu m CMOS comparator to obtain a response time of 43 ns. The offset-cancelled amplifier reduces the input-referred offset so that medium-resolution analog-to-digital converters (ADCs) can be built with this comparator. The use of pipelining within the comparator enables the offset cancellation to be done as the dynamic latch is enabled. Power and area are optimally distributed within the amplifier to minimize response time.<> View full abstract»

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  • A switched-capacitor filter silicon compiler

    Publication Year: 1988 , Page(s): 166 - 174
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1008 KB)  

    The compiler system handles the entire design process from specifications to mask generation, including all necessary simulations. The features of this silicon compiler are: powerful synthesis and simulation programs, complete interactivity, generation programs to create input description files of the simulators, and a unique description of the circuit. One of the main advantages of the system is the drastic reduction in time required for design and verification of such circuits. In addition, it has the security of an integrated system, thus making all backward verifications unnecessary. A test filter entirely designed with the compiler is presented.<> View full abstract»

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  • A monolithic video frequency filter using NIC-based gyrators

    Publication Year: 1988 , Page(s): 175 - 182
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (767 KB)  

    A filter system for analog video signal processing is discussed. This system is composed of a variable time-constant active RC filter part with balanced-type negative impedance converters (NICs) and an automatic tuning circuit part using a PLL. The system is implemented by a conventional junction-isolated 15- mu m bipolar process with n-p-n transistors of f/sub T/=400 MHz; features low production cost; and it uses an automatic tuning scheme with better accuracy in response than previous systems. A filter system with a passband from 3.7 to 5.2 MHz, and which operates from a single 5-V supply, was implemented by the bipolar process. Experimental results obtained for the filter system are given.<> View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Editor-in-Chief
Michael Flynn
University of Michigan