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IEEE Transactions on Computers

Issue 10 • Oct 1989

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Displaying Results 1 - 15 of 15
  • A systematic design of cellular permutation arrays

    Publication Year: 1989, Page(s):1447 - 1451
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    A parametrized design technique is presented of cellular permutation arrays based on coset decompositions of symmetric groups. A type of permutation cell referred to as a coset generator is introduced to customize the propagation delay, fan-in, fan-out, and number of edges in the target network. To aid in the design process, a cost function is derived expressing the number of edges in terms of the... View full abstract»

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  • An algorithm to design finite field multipliers using a self-dual normal basis

    Publication Year: 1989, Page(s):1457 - 1460
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (360 KB)

    The concept of using a self-dual normal basis to design the Massey-Omura finite-field multiplier is presented. An algorithm is given to locate a self-dual normal basis for GF(2m) for odd m. A method to construct the product function for designing the Massey-Omura multiplier is developed. It is shown that the construction of the product function based on a self-dual bas... View full abstract»

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  • A performance bound of multistage combining networks

    Publication Year: 1989, Page(s):1387 - 1395
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    A bound on the delays in multistage combining networks is developed by considering an idealized combining under hot-spot traffic. It is concluded that multistage combining networks are stable, at least in theory, under hot-spot traffic. The author discusses some problems in achieving such stability in practice View full abstract»

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  • Path allocation access control in fiber optic communication systems

    Publication Year: 1989, Page(s):1372 - 1382
    Cited by:  Papers (22)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (692 KB)

    A path-oriented channel allocation management approach is introduced for the emerging high-bandwidth fiber optic star networks. In the proposed approach, the transmission channel of the source node and the reception channel of the destination node are synchronized at the central switching node, creating a virtual path for packet communication between any two nodes. The number of virtual paths that... View full abstract»

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  • Bisectional fault-tolerant communication architecture for supercomputer systems

    Publication Year: 1989, Page(s):1425 - 1446
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1812 KB)

    A highly versatile communication architecture, the bisectional interconnection network, is proposed. These networks possess many attractive features such as small internode distances, ability to do self-routing which is easily extendible to failure conditions, and the capability of maximal fault tolerance. The proposed architecture allows optimal implementation of various logical configurations. F... View full abstract»

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  • Distributed assignment algorithms for multihop packet radio networks

    Publication Year: 1989, Page(s):1353 - 1361
    Cited by:  Papers (139)  |  Patents (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (844 KB)

    New distributed dynamic channel assignment algorithms for a multihop packet radio network are introduced. The algorithms ensure conflict-free transmissions by the nodes of the network. The basic idea of the algorithms is to split the shared channel into a control segment and a transmission segment. The control segment is used to avoid conflicts among nodes and to increase the utilization of the tr... View full abstract»

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  • On systolic contractions of program graphs

    Publication Year: 1989, Page(s):1451 - 1457
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (708 KB)

    A variant of the mapping problem, namely, systolic contractions of program graphs, is considered. The notion of time links is introduced to mechanize the contraction process; the timing of information flow between processors is modeled in terms of fundamental loop and path equations of delays and is optimized using linear programming. While the results apply primarily to systolic contractions, the... View full abstract»

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  • Design of testable VLSI circuits with minimum area overhead

    Publication Year: 1989, Page(s):1460 - 1462
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    One of the techniques used to tackle the increasing complexity of testing VLSI circuits is to incorporate built-in self-test (BIST) structures. However, incorporation of such BIST structures calls for increased area overhead due to additional logic gates and interconnections. It is very important to keep this area overhead to a minimum. The authors present a simple graph model of the area overhead... View full abstract»

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  • Merging and sorting networks with the topology of the omega network

    Publication Year: 1989, Page(s):1396 - 1403
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (716 KB)

    A class of comparator networks obtained from the omega permutation network by replacing each switch with a comparator exchanger of arbitrary direction is considered. These networks are all isomorphic to each other, have merging capabilities, and can be used as building blocks of sorting networks in ways different from the standard merge-sort scheme. It is shown that the bitonic and balanced merger... View full abstract»

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  • A VLSI architecture for fast inversion in GF(2m)

    Publication Year: 1989, Page(s):1383 - 1386
    Cited by:  Papers (64)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (284 KB)

    A new algorithm for performing fast inversion in GF (2 m) is presented. The algorithm requires O[mlog2 m) computation time. Using serial-in-parallel-out multiplication, the design of the algorithm is highly regular, modular, and well suited for VLSI implementation View full abstract»

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  • An optimal shortest-path routing policy for network computers with regular mesh-connected topologies

    Publication Year: 1989, Page(s):1362 - 1371
    Cited by:  Papers (41)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (964 KB)

    A probabilistic routing policy, the Z2 (zigzag) routing policy, is presented within the class of nonadaptive, shortest-path routing policies for regular mesh-connected topologies such as n-dimensional toroids and hypercubes. The focus of the research is routing in networks of computers in a distributed computing environment, where constituent subcomputers are organized... View full abstract»

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  • A binary single-key-lock system for access control

    Publication Year: 1989, Page(s):1462 - 1466
    Cited by:  Papers (12)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (480 KB)

    A binary coding method was invented and has been applied to the single-key-lock (SKL) system which achieves access control by associating with each accesser only one key and with each resource only one lock. The new system is called the binary single-key-lock (BSKL) system. In both the SKL and BSKL systems, through operations on the single-key-lock pair, the control information can be revealed. On... View full abstract»

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  • The transduction method-design of logic networks based on permissible functions

    Publication Year: 1989, Page(s):1404 - 1424
    Cited by:  Papers (139)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1912 KB)

    Based on the new concept of permissible functions, a heuristic procedure to design logic networks with as few gates as possible, without guaranteeing the minimality of designed networks, is developed. This procedure, which is drastically different from conventional logic-design procedures, is called the transduction method, because an initial network designed by any conventionally known logic-desi... View full abstract»

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  • Parallel random number generation for VLSI systems using cellular automata

    Publication Year: 1989, Page(s):1466 - 1473
    Cited by:  Papers (117)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    A novel random number generation (RNG) architecture of particular importance in VLSI for fine-grained parallel processing is proposed. It is demonstrated that efficient parallel pseudorandom sequence generation can be accomplished using certain elementary one-dimensional cellular automata (two binary states per site and only nearest-neighbor connections). The pseudorandom numbers appear in paralle... View full abstract»

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  • On iterative arrays for the Euclidean algorithm over finite fields

    Publication Year: 1989, Page(s):1473 - 1478
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Iterative arrays are described which implement the extended Euclidean algorithm over finite fields with characteristic two and are designed to have throughputs in the area of hundreds of megabits per second. A special form of the Euclidean algorithm is the basis of these arrays, which can be used for error decoding. The propagation time through the array is derived as a function of the degree of t... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org