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IEEE Transactions on Computers

Issue 5 • Date May 1998

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Displaying Results 1 - 9 of 9
  • Theory and design of adjacent asymmetric error masking codes

    Publication Year: 1998, Page(s):544 - 555
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    Recently, Matsuzawa and Fujiwara (1988) proposed a novel scheme to mask line faults of bus line circuits (such as address buses) due to short circuit defects between adjacent lines. In this paper, first we propose the fundamental theory and then present some efficient designs of these codes. Some lower and upper bounds for the optimal codes are also given View full abstract»

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  • Design of balanced and constant weight codes for VLSI systems

    Publication Year: 1998, Page(s):556 - 572
    Cited by:  Papers (16)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    A constant weight, w, code with k information bits and r check bits is a binary code of length n=k+r and cardinality 2k such that the number of 1s in each code word is equal to w. When w=[n/2], the code is called balanced. This paper describes the design of balanced and constant weight codes with parallel encoding and parallel decoding. Infinite families of efficient constant weight cod... View full abstract»

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  • CPU cache prefetching: Timing evaluation of hardware implementations

    Publication Year: 1998, Page(s):509 - 526
    Cited by:  Papers (18)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (612 KB)

    Prefetching into CPU caches has long been known to be effective in reducing the cache miss ratio, but known implementations of prefetching have been unsuccessful in improving CPU performance. The reasons for this are that prefetches interfere with normal cache operations by making cache address and data ports busy, the memory bus busy, the memory banks busy, and by not necessarily being complete b... View full abstract»

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  • Architecture scalability of parallel vector computers with a shared memory

    Publication Year: 1998, Page(s):614 - 624
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (168 KB)

    Based on a model of a parallel vector computer with a shared memory, its scalability properties are derived. The processor-memory interconnection network is assumed to be composed of crossbar switches of size b×b. This paper analyzes sustainable peak performance under optimal conditions, i.e., no memory bank conflicts, sufficient processor-memory bank pathways, and no interconnection network... View full abstract»

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  • A configurable membership service

    Publication Year: 1998, Page(s):573 - 586
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    A membership service is used to maintain information about which sites are functioning in a distributed system at any given time. Many such services have been defined, with each implementing a unique combination of properties that simplify the construction of higher levels of the system. Despite this wealth of possibilities, however, any given service typically realizes only one set of properties,... View full abstract»

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  • An efficient solution to the cache thrashing problem caused by true data sharing

    Publication Year: 1998, Page(s):527 - 543
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (508 KB)

    When parallel programs are executed on multiprocessors with private caches, a set of data may be repeatedly used and modified by different threads. Such data sharing can often result in cache thrashing, which degrades memory performance. This paper presents and evaluates a loop restructuring method to reduce or even eliminate cache thrashing caused by true data sharing in nested parallel loops. Th... View full abstract»

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  • A performance study of instruction cache prefetching methods

    Publication Year: 1998, Page(s):497 - 508
    Cited by:  Papers (8)  |  Patents (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    Prefetching methods for instruction caches are studied via trace-driven simulation. The two primary methods are “fall-through” prefetch (sometimes referred to as “one block lookahead”) and “target” prefetch. Fall-through prefetches are for sequential line accesses, and a key parameter is the distance from the end of the current line where the prefetch for the ne... View full abstract»

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  • Double step branching CORDIC: a new algorithm for fast sine and cosine generation

    Publication Year: 1998, Page(s):587 - 602
    Cited by:  Papers (22)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (536 KB)

    Duprat and Muller (1993) introduced the ingenious “Branching CORDIC” algorithm. It enables a fast implementation of CORDIC algorithm using signed digits and requires a constant normalization factor. The speedup is achieved by performing two basic CORDIC rotations in parallel in two separate modules. In their method, both modules perform identical computation except when the algorithm i... View full abstract»

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  • Damage assessment for optimal rollback recovery

    Publication Year: 1998, Page(s):603 - 613
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Conventional schemes of rollback recovery with checkpointing for concurrent processes have overlooked an important problem: contamination of checkpoints as a result of error propagation among the cooperating processes. Error propagation is unavoidable due to imperfect detection mechanisms and random interprocess communications, and it could give rise to contaminated checkpoints which, in turn, res... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org