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IEE Proceedings - Computers and Digital Techniques

Issue 1 • Date Jan 1998

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Displaying Results 1 - 11 of 11
  • Balanced Boolean functions

    Publication Year: 1998, Page(s):52 - 62
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1056 KB)

    Many common logic circuits such as adders, parity checkers and multiplexers realise Boolean functions that are true for exactly half their input combinations, and false for the other half; we refer to such functions as balanced. Recently, these functions have been shown to be very useful for testing logic circuits, and for data encryption in cryptography. Here, we present a general theory of balan... View full abstract»

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  • Two's complement division without using the set of full precision comparisons

    Publication Year: 1998, Page(s):19 - 26
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (840 KB)

    It is well known that the existing two's complement radix-2k division methods require a set of full wordlength comparisons of the multiples of the divisor against the shifted remainder. For fast division, these comparisons should be implemented in parallel. Therefore, a huge area is required to implement such high radix division. The paper presents a novel two's complement radix-2... View full abstract»

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  • Signature schemes based on factoring and discrete logarithms

    Publication Year: 1998, Page(s):33 - 36
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    The paper proposes two new digital signature schemes, the security of which is based on the difficulties of computing discrete logarithms and factoring, the performance of which is similar to those of the original ElGamal signature scheme and the Harn signature scheme. The paper also considers some possible attacks, and shows that the two schemes are more secure than the original ElGamal signature... View full abstract»

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  • Logic synthesis for a fine-grain FPGA

    Publication Year: 1998, Page(s):47 - 51
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (508 KB)

    The paper describes an algorithm which combines logic synthesis and technology mapping specifically for Xilinx's XC6200, a new family of fine-grain, dynamically reconfigurable FPGA. The algorithm employs a BDD representation of the logic function and a genetic algorithm (GA) is used to find a good decomposition variable ordering. The algorithm also exploits the architectural features of the XC6200... View full abstract»

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  • Efficient group signature scheme based on the discrete logarithm

    Publication Year: 1998, Page(s):15 - 18
    Cited by:  Papers (9)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (376 KB)

    Group signatures, introduced by D. Chaum and E. Van Heyst (1991), allow individual members to make signatures on behalf of the group while providing anonymity. All previously proposed schemes, as far as we know, are not very efficient in terms of computational, communication and storage costs. In the paper, we describe a novel group signature that is used to reflect and project the actual needs ar... View full abstract»

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  • Empirical study of memory-data: characteristics and compressibility

    Publication Year: 1998, Page(s):63 - 67
    Cited by:  Papers (10)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (528 KB)

    The authors present results from an investigation into the characteristics of memory-data in Unix applications. The memory-data analysis shows a number of surprising characteristics and reveals substantial similarities across applications. It is also shown that memory-data typically compresses to half the original volume. The characteristics of the memory-data, as well as the results on compressio... View full abstract»

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  • Creating a highly reliable modified gamma interconnection network using a balance approach

    Publication Year: 1998, Page(s):27 - 32
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (592 KB)

    An interconnection network with redundant paths is desirable for high-performance multiprocessor systems owing to its ability to tolerate faults by routing requests through alternative paths. The gamma interconnection network (GIN) provides a unique path from any source (S) to a destination (D) when S equals D and the multiple paths between certain (S, D) pairs share a single common route for many... View full abstract»

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  • Efficient bipartitioning algorithm for size-constrained circuits

    Publication Year: 1998, Page(s):37 - 46
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (892 KB)

    A novel module-migration bipartitioner (MMP) for VLSI circuits is proposed. MMP uses an efficient module migration process, which can relax the size constraints temporarily and intensify the capability of escaping from local optima, as its iterative improvement mechanism. Besides evaluating the same module gain when performing the Fiduccia-Mattheyses (FM) algorithm for selecting the module to move... View full abstract»

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  • Design and analysis of asynchronous adders

    Publication Year: 1998, Page(s):1 - 8
    Cited by:  Papers (7)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1400 KB)

    An asynchronous adder can take advantage of the shorter carry propagation chains that occur in practice and exhibit a data-dependent computation delay. Basically, an asynchronous adder has a mechanism to announce early completion by detecting when it is done. Such an adder is extremely useful in asynchronous implementation of computing structures. In this paper we evaluate the designs tradeoffs of... View full abstract»

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  • Deadlock detection using (0, 1)-labelling of resource allocation graphs

    Publication Year: 1998, Page(s):68 - 72
    Cited by:  Papers (3)  |  Patents (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (484 KB)

    A deadlock detection method based on the use of the resource allocation graph is presented. The method is different from the existing deadlock avoidance techniques in that the original directed resource allocation graph is first transformed into an undirected (0 1)-labelled graph in which the deadlock would occur only if a cycle has been labelled alternatingly with 0s and 1s. The algorithm is appl... View full abstract»

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  • Image component labelling on the star graph using divide and conquer

    Publication Year: 1998, Page(s):9 - 14
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (628 KB)

    Since its introduction in the literature, the star interconnection network has become a popular architecture for connecting parallel processors. It compares favourably with the famous hypercube as far as basic network attributes are concerned. Its degree and diameter are sublogarithmic with respect to the total number of processors and it enjoys fault tolerance and symmetry properties. It remains ... View full abstract»

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