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IEE Proceedings - Computers and Digital Techniques

Issue 2 • Date Mar 1998

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Displaying Results 1 - 11 of 11
  • Recursive relations and fast flow diagram for nonlinear quantised transform

    Publication Year: 1998, Page(s):97 - 107
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (888 KB)

    A nonlinear quantised transform called a sign transform is introduced. Besides transforming uniquely between ternary data and the ternary spectral domain, the transform also converts to and from the sign Haar and sign Walsh spectral domains. Recursive equations defining forward and inverse transforms are presented. It is possible to calculate the new transform using recursive definitions of a new ... View full abstract»

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  • Authenticated encryption scheme with (t, n) shared verification

    Publication Year: 1998, Page(s):117 - 120
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (408 KB)

    A new authenticated encryption scheme with (t, n) shared verification based on discrete logarithms is proposed. In the scheme any ciphertext of signature for a message is addressed to a specified group of verifiers in such a way that the ability to decrypt the ciphertext of signature is regulated by the adopted (t, n) threshold scheme. That is, any t out of n verifiers in the group share the respo... View full abstract»

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  • Datapath layout optimisation using genetic algorithm and simulated annealing

    Publication Year: 1998, Page(s):135 - 141
    Cited by:  Papers (4)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (696 KB)

    The paper deals with the minimisation of the track density and the interconnection delay in the design of a high-performance compact datapath. The authors applied a hybrid approach of genetic algorithm (GA) and simulated annealing (SA) to determine the optimal datapath element ordering to minimise both the track density and the wire length. To improve the computation speed, they used the datapath-... View full abstract»

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  • Static power analysis for power-driven synthesis

    Publication Year: 1998, Page(s):89 - 95
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (676 KB)

    A new static power analysis method for CMOS combinational circuits is presented. This approach integrates the simulation-based method and the probabilistic method. And can establish the relationships between the primary inputs and the internal nodes in the circuit. Based on the relationships, our approach can also indicate which internal node or input sequence consumes the most power. It is thus s... View full abstract»

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  • Digit-serial systolic multiplier for finite fields GF(2m)

    Publication Year: 1998, Page(s):143 - 148
    Cited by:  Papers (18)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (536 KB)

    A new digit-serial systolic array is proposed for computing multiplications in finite fields GF(2m) with the standard basis representation. If input data come in continuously the proposed array can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. Each cell of the array can be further pipelined so that the maximum propagation d... View full abstract»

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  • Theory and design of SEC-DED-AUED codes

    Publication Year: 1998, Page(s):121 - 126
    Cited by:  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (472 KB)

    To construct a single error correcting/double error detecting/all unidirectional error detecting (SEC-DED-AUED) codes a common method is to choose a SEC-DED code and then append a stream of extra bits such that the new code can detect all the unidirectional errors. An efficient method for constructing a class of SEC-DED-AUED codes is presented. The encoding/decoding algorithms proposed with this m... View full abstract»

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  • Embedding meshes and TORUS networks onto degree-four chordal rings

    Publication Year: 1998, Page(s):73 - 80
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (712 KB)

    Degree-four chordal rings demonstrate many attractive properties, such as node symmetry, constant degree, O(√N) diameter and the ability to interconnect an arbitrary number of nodes. The authors study the abilities of degree-four chordal rings to execute parallel programs using graph-embedding techniques. Since many algorithms have been designed for meshes and TORUS networks, the issue of em... View full abstract»

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  • Design for the discrete cosine transform in VLSI

    Publication Year: 1998, Page(s):127 - 133
    Cited by:  Papers (5)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (700 KB)

    The discrete cosine transform is reviewed with the aid of recent implementations of the 8×8 transform. The distinct roles of algorithmic and multiplier design are identified, and key circuit and logic innovations are highlighted View full abstract»

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  • Designs for self checking flip-flops

    Publication Year: 1998, Page(s):81 - 88
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (624 KB)

    The authors introduce two low-cost, modular, totally self checking (TSC), edge triggered and error propagating (code disjoint) flip-flops: one, a D flip-flop used in TSC and strongly fault secure (SFS) synchronous circuits with two-rail codes, the other a T flip-flop, used in a similar way as the D flip-flop but retaining the error as an indicator until the next presetting, to aid error propagatio... View full abstract»

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  • Hardware-supported asynchronous checkpointing scheme

    Publication Year: 1998, Page(s):109 - 115
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (876 KB)

    The authors propose a hardware-supported scheme to facilitate fast checkpointing and failure recovery operations. The mechanism uses a small-sized bank of nonvolatile memory to save an incremental checkpoint for a processor so that the time overhead incurred by checkpointing can be reduced. Parity technique is employed to compress checkpointing information. An important feature of our scheme is th... View full abstract»

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  • Cryptanalysis and improvement of signcryption schemes

    Publication Year: 1998, Page(s):149 - 151
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (280 KB)

    In 1997, two new schemes for authenticated encryption, called signcryption, were proposed by Zheng. In the paper, the authors point out a serious problem with these schemes. In fact, the way to gain nonrepudiation violates the confidentiality. The authors compare the schemes to previously known authenticated encryption schemes which were not mentioned by Zheng. Finally, the authors outline a solut... View full abstract»

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