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Computers and Digital Techniques, IEE Proceedings -

Issue 2 • Date Mar 1998

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Displaying Results 1 - 11 of 11
  • Designs for self checking flip-flops

    Page(s): 81 - 88
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The authors introduce two low-cost, modular, totally self checking (TSC), edge triggered and error propagating (code disjoint) flip-flops: one, a D flip-flop used in TSC and strongly fault secure (SFS) synchronous circuits with two-rail codes, the other a T flip-flop, used in a similar way as the D flip-flop but retaining the error as an indicator until the next presetting, to aid error propagation. Thus, the self checking T flip-flop can be used as an error indicator. The self checking D flip-flop is smaller than the duplicate D flip-flop circuitry by 30%. The self checking T flip-flop error indicator is 60% smaller than the pervious error indicator in the literature. These circuits, unlike previously reported circuits, can also detect stuck-at faults in the clock inputs. The authors have also presented TSC/error propagating applications for the above flip-flops: a counter and a shift register View full abstract»

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  • Authenticated encryption scheme with (t, n) shared verification

    Page(s): 117 - 120
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (408 KB)  

    A new authenticated encryption scheme with (t, n) shared verification based on discrete logarithms is proposed. In the scheme any ciphertext of signature for a message is addressed to a specified group of verifiers in such a way that the ability to decrypt the ciphertext of signature is regulated by the adopted (t, n) threshold scheme. That is, any t out of n verifiers in the group share the responsibility (or authority) for message recovery. The proposed scheme preserves the merits inherent in the signature scheme with message recovery and the (t, n) shared verification scheme. As compared to Harn's (t, n) shared verification scheme and its further modifications. The proposed scheme has the following advantages: it requires smaller bandwidth and achieves more secrecy of data transmission: it is more efficient for signature verification View full abstract»

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  • Digit-serial systolic multiplier for finite fields GF(2m)

    Page(s): 143 - 148
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (536 KB)  

    A new digit-serial systolic array is proposed for computing multiplications in finite fields GF(2m) with the standard basis representation. If input data come in continuously the proposed array can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. Each cell of the array can be further pipelined so that the maximum propagation delay can be kept small to maintain a high clock rate when the digit size L gets large. The proposed architecture possesses the features of regularity, modularity, and unidirectional data flow. It is thus well suited to VLSI implementation with fault-tolerant design. As compared with existing bit-serial and bit-parallel multipliers for GF(2m), the proposed digit-serial architecture gains an advantage in terms of improving the trade-off between throughput performance and hardware complexity View full abstract»

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  • Recursive relations and fast flow diagram for nonlinear quantised transform

    Page(s): 97 - 107
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (888 KB)  

    A nonlinear quantised transform called a sign transform is introduced. Besides transforming uniquely between ternary data and the ternary spectral domain, the transform also converts to and from the sign Haar and sign Walsh spectral domains. Recursive equations defining forward and inverse transforms are presented. It is possible to calculate the new transform using recursive definitions of a new type of matrix called a sign matrix. New properties of, and operations on, such a type of matrix are shown. The fast flow diagram for efficient calculation of the new transform is introduced, implemented in the form of a locally connected flexible parallel architecture. The computational advantages of new algorithms developed for sign transforms and their comparison with known fast sign Haar and fast sign Walsh transforms are also discussed View full abstract»

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  • Cryptanalysis and improvement of signcryption schemes

    Page(s): 149 - 151
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    In 1997, two new schemes for authenticated encryption, called signcryption, were proposed by Zheng. In the paper, the authors point out a serious problem with these schemes. In fact, the way to gain nonrepudiation violates the confidentiality. The authors compare the schemes to previously known authenticated encryption schemes which were not mentioned by Zheng. Finally, the authors outline a solution that helps to overcome the problem View full abstract»

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  • Embedding meshes and TORUS networks onto degree-four chordal rings

    Page(s): 73 - 80
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (712 KB)  

    Degree-four chordal rings demonstrate many attractive properties, such as node symmetry, constant degree, O(√N) diameter and the ability to interconnect an arbitrary number of nodes. The authors study the abilities of degree-four chordal rings to execute parallel programs using graph-embedding techniques. Since many algorithms have been designed for meshes and TORUS networks, the issue of embedding meshes and TORUS networks onto degree-four chordal rings is addressed. Mapping functions, simple and snake-like, of embedding meshes and TORUS networks onto the degree-four chordal rings is discussed in detail. It is shown that the ILLIAC network is a special class of the degree-four chordal ring. Topological properties are investigated, such as diameter and average distance of ILLIAC networks and optimal degree-four chordal rings, another special class of degree-four chordal rings. Comparisons of ILLIAC networks and optimal chordal rings in these embedding issues are given View full abstract»

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  • Datapath layout optimisation using genetic algorithm and simulated annealing

    Page(s): 135 - 141
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (696 KB)  

    The paper deals with the minimisation of the track density and the interconnection delay in the design of a high-performance compact datapath. The authors applied a hybrid approach of genetic algorithm (GA) and simulated annealing (SA) to determine the optimal datapath element ordering to minimise both the track density and the wire length. To improve the computation speed, they used the datapath-specific genetic operators. Experimental results for the `real-world' microprocessor examples show that the GA/SA hybrid approach outperforms the existing genetic approaches and gives similar results to simulated annealing with much less computation time View full abstract»

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  • Theory and design of SEC-DED-AUED codes

    Page(s): 121 - 126
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (472 KB)  

    To construct a single error correcting/double error detecting/all unidirectional error detecting (SEC-DED-AUED) codes a common method is to choose a SEC-DED code and then append a stream of extra bits such that the new code can detect all the unidirectional errors. An efficient method for constructing a class of SEC-DED-AUED codes is presented. The encoding/decoding algorithms proposed with this method can be implemented with simple and fast hardware. In a ROM-based implementation it results in significant saving of word length View full abstract»

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  • Hardware-supported asynchronous checkpointing scheme

    Page(s): 109 - 115
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (876 KB)  

    The authors propose a hardware-supported scheme to facilitate fast checkpointing and failure recovery operations. The mechanism uses a small-sized bank of nonvolatile memory to save an incremental checkpoint for a processor so that the time overhead incurred by checkpointing can be reduced. Parity technique is employed to compress checkpointing information. An important feature of our scheme is that the checkpointing operation is dissociated from the parity update action. As a result, checkpointing latency is not affected by the speed of parity update activities, and thus is reduced. Moreover. It does not require atomic action for updating the parity data. Furthermore, our scheme allows each processor to initiate a checkpoint independently of others. Experimental results show that the overhead of our mechanism is small, and is not sensitive to the number of checkpoints taken by the processors. This observation suggests that the proposed hardware-supported scheme is promising for improving the performance of checkpoint/rollback-recovery systems View full abstract»

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  • Design for the discrete cosine transform in VLSI

    Page(s): 127 - 133
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (700 KB)  

    The discrete cosine transform is reviewed with the aid of recent implementations of the 8×8 transform. The distinct roles of algorithmic and multiplier design are identified, and key circuit and logic innovations are highlighted View full abstract»

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  • Static power analysis for power-driven synthesis

    Page(s): 89 - 95
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (676 KB)  

    A new static power analysis method for CMOS combinational circuits is presented. This approach integrates the simulation-based method and the probabilistic method. And can establish the relationships between the primary inputs and the internal nodes in the circuit. Based on the relationships, our approach can also indicate which internal node or input sequence consumes the most power. It is thus suitable for performing power estimation in the synthesis environment for power optimisation. To the best of our knowledge, this is the first attempt to develop a systematic way to symbolically represent the relationships between the primary inputs and the power consumption at every internal node of a circuit. Furthermore, by using the existing piecewise linear delay model, as well as the proposed algorithm, this novel method is also very accurate and efficient. For a set of benchmark circuits, the experimental results show that the power estimated by our technique is within 5% error as compared with that by the exact SPICE simulation, while the execution speed is more than four orders of magnitude faster View full abstract»

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