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Circuits, Devices and Systems, IEE Proceedings -

Issue 2 • Date Apr 1998

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Displaying Results 1 - 14 of 14
  • Novel MOSFET-C continuous-time oscillator with precision amplitude control and self-start

    Page(s): 90 - 94
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (620 KB)  

    A novel MOSFET-C state variable oscillator is proposed. The circuit integrated in a 0.8 μm CMOS process provides precision control of both amplitude and frequency and is guaranteed to start oscillating. This readily integrable audio frequency, sinusoidal oscillator can achieve very low harmonic distortion. The experimental results are in accordance with the predicted theoretical behaviour View full abstract»

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  • Analysis of self-excited electronic ballasts using BJTs/MOSFETs as switching devices

    Page(s): 95 - 104
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (848 KB)  

    Self-excited electronic ballasts are analysed and compared using the same circuit configuration but two different switching devices, BJTs and MOSFETs. These two different charge driven switching devices normally result in different circuit behaviour and design. According to the operating points of saturable driving transformers and switching devices, a complete circuit operation is divided into six stages. Based on the charge control analysis, the effects of switching devices on the self-excited ballasts are discriminated and evaluated. The analysis reveals that BJTs are more suitable than MOSFETs in this transformer-driven self-excited ballast circuit, and it also provides a clear insight into the utilisation of switching devices View full abstract»

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  • Time-domain fault diagnosis of analogue circuits in the presence of noise

    Page(s): 125 - 131
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (564 KB)  

    An approach to multiple fault diagnosis in dynamic linear and nonlinear circuits based on testing of actual and simulation of nominal circuit is presented. Time domain integral sensitivity is used for constructing test equations. An adaptive algorithm for selecting time intervals for integral sensitivity is included. The least squares approach (LSA) to solve overdetermined diagnosis equations with noisy data is used in conjunction with the regularisation method of Tikhonov. Three illustrative examples show applications of the method View full abstract»

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  • Square-rooting and vector summation circuits using current conveyors

    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (44 KB)  

    Recently, Lui [1995] presented a square-rooting circuit using CCII, MOS transistors and a buffered unity-gain inverting amplifier. It is interesting since it finds various applications as described in his paper. However, an error occurred in the paper. An ambiguity about the polarity of the output will occur in practice. In fact, the racing condition of currents through both MOS transistors will determine the output polarity of the circuit, which is random. It will be troublesome in actual applications and this ambiguity must be eliminated. To overcome this ambiguity, we suggest adding the full wave rectifier to either the output of the buffered inverting amplifier or the z-terminal of the CCII View full abstract»

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  • State variable synthesis of single resistance controlled grounded capacitor oscillators using only two CFOAs

    Page(s): 135 - 138
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    The authors have previously presented a state variable synthesis approach to derivation of current feedback op-amp (CFOA) based single-resistance-controlled oscillators (Senani and Gupta, 1997). An extension of the previous approach is presented to facilitate the derivation of a number of new SRCO circuits which require no more than two CFOAs View full abstract»

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  • Modelling of semiconductor laser amplifier for the terahertz optical asymmetric demultiplexer

    Page(s): 61 - 65
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (392 KB)  

    A semiconductor laser amplifier (SLA) may be used as a nonlinear element in ultrafast optical asymmetric demultiplexers. For demultiplexing to take place in the optical domain it is necessary to create a switching window by placing the SLA asymmetrically in an optical loop and saturating it with a short duration control pulse. The exact size of this window, for selecting the required pulse at the output port, depends mainly on the precise location of the SLA within the loop. In the paper a finite length model of an SLA, used as a switching gate within the loop is presented and results for the carrier density, gain and phase time responses together with transmission (switching) windows are also given. The result obtained for the latter is compared with practical data View full abstract»

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  • Four-quadrant analogue CMOS multiplier cell for VLSI signal and information processing

    Page(s): 132 - 134
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (264 KB)  

    A CMOS four-quadrant analogue multiplier cell for VLSI signal and information processing based on a transconductor and associated circuitry to cancel nonidealities is presented. It is designed to operate in the triode region. This multiplier is modular, has a large dynamic input range, high linearity, low power dissipation and can provide either a differential output current or voltage. The design was fabricated using a 1.2 μm CMOS process. Simulation and experimental results are presented and discussed View full abstract»

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  • Current-dependent collector resistance of the bipolar transistor in quasi-saturation

    Page(s): 66 - 70
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    The analytical collector resistance model is derived from device physics. The MEDICI simulation is employed to justify the assumptions used in the model derivation. The high-current collector current spreading effect on the collector resistance is accounted for, and the predictions of the collector current, using the current-dependent collector resistance model are compared with the experimental data. Good agreement between the model predictions and experimental data has been obtained View full abstract»

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  • S2I first-order incremental A/D converter

    Page(s): 78 - 84
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (796 KB)  

    An incremental analogue-to-digital converter (ADC), designed as part of the signal conditioning circuitry of a pressure sensor interface, is presented. For technological compatibility, the switched-current (SI) technique has been used, which does not need a double polysilicon CMOS process. To reduce the influence of the nonidealities of this technique. A conversion algorithm with digital correction has been chosen and circuit enhancements have been sought. A first 1 μm CMOS prototype has been tested in the laboratory. And a resolution up to 9 bits has been obtained for a 1 MHz clock View full abstract»

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  • Multidimensional signal-noise neural network model

    Page(s): 111 - 117
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (476 KB)  

    Signal and noise behaviours of microwave transistors are modelled through the neural network approach for the whole operating ranges including frequency, bias and configuration types. Here, the device is modelled by a black box whose small-signal and noise parameters are evaluated through a neural network based upon the fitting of both of these parameters for multiple bias and configuration. The concurrent modelling procedure does not require the solving of device physics equations repeatedly during optimisation, and by this type of modelling the signal (S) and noise (N) parameters can be predicted not only at a single operation frequency around the chosen bias condition for a configuration, but at the same time for the whole operation frequency band for the same operating conditions, with good agreement compared to the measurements View full abstract»

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  • New current conveyor for high-speed low-power current sensing

    Page(s): 85 - 89
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (592 KB)  

    A novel low-voltage current conveyor for fast CMOS SRAM applications is presented. The sensing speed is independent of the bit-line capacitances and a positive feedback technique is employed to give the circuit a high-speed and low-power operation. Performance evaluation has shown that, based on equal area ratios, the new conveyor outperforms the conventional circuit in terms of speed and average power dissipation by at least 30%. The static behaviour of the basic circuit is analysed. HSPICE simulations have been used to characterise the circuits. Experimental results have verified the functionality of the new circuit and its superiority over the conventional CMOS current conveyor View full abstract»

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  • Quaternary voltage-mode CMOS circuits for multiple-valued logic

    Page(s): 71 - 77
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (556 KB)  

    A set of novel voltage-mode CMOS circuits for the implementation of multiple-valued logic (MVL) systems is introduced. The circuit level implementation of the multiple-valued logic operators: logical sum, logical product, level-up, level-down and level conversions are presented. The mathematical properties of the latter operator are formally proved, The proposed multiple-valued logic circuits exhibit zero static power consumption, do not use clocking, and function on any arithmetic base. The proposed circuits consist of appropriately constructed enhancement-mode and depletion-mode 1.5 μm MOSFETs. Simulation of the introduced quaternary logic voltage-mode CMOS circuits, using SPICE, indicates improved performance (higher speeds) compared to existing ones View full abstract»

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  • GA-based design of multiplierless 2-D state-space digital filters with low roundoff noise

    Page(s): 118 - 124
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (688 KB)  

    A new design method for multiplierless two-dimensional (2-D) state-space digital filters (SSDFs) with very low roundoff noise is presented. To eliminate multipliers in the hardware implementation, multiplierless 2-D SSDFs are designed under the constraint that all coefficients are expressed as one or two powers-of-two terms. They are attractive for low-cost implementation and high-speed operation. In addition, they can also perform highly accurate 2 D digital filtering because of very low roundoff noise. A combinatorial optimisation method based on a genetic algorithm (GA) is given to determine the coefficients. A stability test routine is also embedded in the GA-based design procedure to ensure the stability of the resultant multiplierless SSDFs. The proposed method can design multiplierless 2-D SSDFs not only with small approximation error but also with almost minimum roundoff noise. In addition they require fewer computational volume than 2-D SSDFs designed in a continuous coefficient space. For 16-bit words, the designed multiplierless 2-D SSDFs can be implemented with 24%, of the computational volume of 2-D SSDFs with real multipliers. The effectiveness of the proposed methods is demonstrated by two design examples View full abstract»

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  • MOS and bipolar gated thyristor: a thyristor with IGBT switching characteristics

    Page(s): 105 - 110
    Save to Project icon | Click to expandQuick Abstract | PDF file iconPDF (716 KB)  

    The IGBT has become the device of choice in many high-voltage-power electronic applications, by virtue of combining the ease of MOS gate control with an acceptable forward voltage drop. However, designers have retained an interest in MOS gated thyristor structures which have a turn-off capability. These offer low on-state losses as a result of their latching behaviour. Recently, there have been various proposals for dual-gate devices that have a thyristor on-state with IGBT-like switching. Many of these dual gated structures rely on advanced MOS technology with inherent manufacturing difficulties. The MOS and bipolar gated thyristor offers all the advantages of dual gated performance, while employing standard IGBT processing techniques. The paper describes the MBGT in detail, and presents experimental and simulation results for devices based on realistic commercial processes. It is shown that the MBGT represents a viable power semiconductor device technology, suitable for a diverse range of applications View full abstract»

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