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Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Issue 5 • Date May 1998

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Displaying Results 1 - 18 of 18
  • Guest Editorial - Introduction To The Special Issue On Iscas'97

    Page(s): 533 - 534
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    Freely Available from IEEE
  • Repeater design to reduce delay and power in resistive interconnect

    Page(s): 607 - 616
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    In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current, In order to develop a repeater design methodology, a timing model characterizing a complementary metal-oxide-semiconductor (CMOS) inverter driving a resistance-capacitance (RC) load is presented. The model is based on the Sakurai short-channel α-power law model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining the optimum number of uniformly sized repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical RC loads, this analytical repeater model exhibits a maximum error of 16% as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized repeaters versus tapered-buffer repeaters is also investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffers and tapered-buffer repeaters even with relatively small resistive RC loads. An expression for the short-circuit power dissipation of a repeater driving an RC load is presented, A comparison of the short-circuit power dissipation to the dynamic power dissipation in repeater chains and related power/delay tradeoffs are made View full abstract»

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  • A linear integrated LC bandpass filter with Q-enhancement

    Page(s): 635 - 639
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    A technique is proposed in this paper for linearizing active Q-enhanced monolithic LC filters. This technique employs capacitive dividers and tunable linear transconductors. Various multi-tanh translinear circuits can be used to implement the linear transconductors, taking into consideration the need for linear operating range and the low supply voltage. A linear Q-enhanced LC filter using the proposed technique has been implemented in a 0.5 μm bipolar process. The demonstrated filter chip operates at a center frequency around 1 GHz with the quality factor tunable up to 400 without spurious oscillation. For a Q of 40, the input intercept point and spurious-free dynamic range are -6.67 dBm and 36 dB, respectively, at a power consumption of 68 mW and with 7 dB of gain View full abstract»

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  • A study of stratified sampling in variance reduction techniques for parametric yield estimation

    Page(s): 575 - 583
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    The Monte Carlo (MC) method exhibits generality and insensitivity to the number of stochastic variables, but is expensive for accurate yield estimation of electronic circuits. In the literature, several variance reduction techniques have been described, e.g., stratified sampling. In this contribution the theoretical aspects of the partitioning scheme of the tolerance region in stratified sampling is presented. Furthermore, a theorem about the efficiency of this estimator over the primitive MC (PMC) estimator versus sample size is given. To the best of our knowledge, this problem was not previously studied in parametric yield estimation. In this method we suppose that the components of parameter disturbance space are independent or can be transformed to an independent basis. The application of this approach to a numerical example (Rosenbrock's curved-valley function) and a circuit example (Sallen-Key low-pass filter) are given View full abstract»

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  • MMIC active filter with tuned transversal element

    Page(s): 632 - 634
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    A novel GaAs monolithic microwave integrated circuit (MMIC) active filter structure based on the lumped and transversal technique is proposed for operation in the X-band. This new structure includes a tuned amplifier as transversal element of the filter in order to improve the band-edge rejection. A design example of a bandpass filter centered at 7.5 GHz with 2 dB passband ripple and 30 dB rejection at 1 GHz apart from passband edges is presented in terms of computer simulations and layout. The simulated results demonstrate its superior performance when compared with the traditional lumped and transversal technique View full abstract»

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  • Current-mode approach for wide-gain bandwidth product architecture

    Page(s): 626 - 631
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    This paper describes the architectures of a fully differential input/single-ended output wide-band high-gain current-mode comparator and amplifier. Both architectures employ a current conveyor as the primary means of current-mode operation. The proposed comparator circuit delivers extremely high gain and wide bandwidth by employing cascode complementary gain stages and feedforward compensation techniques, respectively. The closed-loop voltage amplifier, using the proposed current-mode techniques, can improve upon the gain-bandwidth product when compared to conventional voltage-mode techniques. Computer simulation results show 135 dB of gain and 100 MHz bandwidth for such an amplifier View full abstract»

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  • Application of singularity detection for the deblocking of JPEG decoded images

    Page(s): 640 - 644
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    The blocking effect is considered as the most disturbing artifact of JPEG decoded images. Many researchers have suggested various methods to tackle this problem. Recently, the wavelet transform modulus maxima (WTMM) approach was proposed and gives a significant improvement over the previous methods in terms of signal-to-noise ratio (SNR) and visual quality. However, the WTMM deblocking algorithm is an iterative algorithm that requires a long computation time to reconstruct the processed WTMM to obtain the deblocked image. In this work, a new wavelet-based algorithm for JPEG image deblocking is proposed. The new algorithm is based on the idea that besides using the WTMM, the singularity of an image can also be detected by computing the sums of the wavelet coefficients inside the so-called “directional cone of influence” in different scales of the image. The new algorithm has the advantage over the WTMM approach in that it can effectively identify the edge and smooth regions of an image irrespective of the discontinuities introduced by the blocking effect. It is an improvement over the WTMM approach in that only a simple inverse wavelet transform is required to reconstruct the processed wavelet coefficients to obtain the deblocked image. As with the WTMM approach, the new algorithm gives consistent and significant improvement over the previous methods for JPEG image deblocking View full abstract»

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  • A formal technique for hardware interface design

    Page(s): 584 - 591
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    In this paper, we consider the problem of hardware interface design in a codesign approach for real-time digital signal processing (DSP) applications. We refer to the hardware component as ASICS (Applied Specific Integrated Circuits) and the software component as processors. We describe a formal technique to communication synthesis starting from hardware I/O transfer sequences computed by a high level synthesis tool, like GAUT. The original nature of our work is the fact that a communication interface is generated at the same time as the hardware module which leads to better performance and optimization and ensures communication data coherency. Our design strategy starts from the hardware I/O transfer sequences computed by GAUT. It incorporates some interface specification (I/O transfer order, timing constraints) obtained by any cosynthesis tool. The proposed allocation procedure of necessary storage components needed for data communication between hardware-software components assigns for each I/O data a time interval at which its transfer could occur. As an illustration, we present a mixed implementation of the GMDF alpha algorithm, an adaptive filter well suited to acoustic echo cancellation, on both ASIC and TS320C40 DSP View full abstract»

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  • An analog VLSI chip with asynchronous interface for auditory feature extraction

    Page(s): 600 - 606
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    We present an analog VLSI chip intended to serve as a front end of a speech recognition system. The chip architecture is inspired by biological auditory models common to humans and primate vertebrates. We include experimental results on a 1.2-μm CMOS custom analog VLSI implementation and speech recognition results obtained from software simulations of the hardware on the TI-DIGITS database View full abstract»

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  • New architectures for M4R shape coding

    Page(s): 556 - 562
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    New architectures for M4R shape encoding and decoding are presented. The M4R method encodes the changing pixels in boundary blocks of two-dimensional shapes. Pipelined architectures for encoding and decoding which reduce memory access, use customized hardware to accelerate critical components, require little external control, and can be easily parallelized are described View full abstract»

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  • A complete pipelined parallel CORDIC architecture for motion estimation

    Page(s): 653 - 660
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    In this paper, a novel fully pipelined parallel CORDIC architecture is proposed for motion estimation. Unlike other block matching structures, it estimates motion in the discrete cosine transform (DCT) domain instead of the spatial domain. As a result, it achieves high system throughput and low hardware complexity as compared to the conventional motion estimation design in MPEG standards. That makes the proposed architecture very attractive in real-time high-speed video communication. Importantly, the DCT-based nature enables us not only to efficiently combine DCT and motion estimation units into a single component but also to replace all multiply-and-add operations in plane rotation by CORDICs to gain further savings in hardware complexity. Furthermore, this multiplier-free architecture is regular, modular, and has solely local connection suitable for VLSI implementation. The goal of the paper is to provide a solution for MPEG compatible video codec design on a dedicated single chip View full abstract»

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  • New adaptive algorithms based on multi-band decomposition of the error signal

    Page(s): 592 - 599
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    New adaptive algorithms based on multi-band decomposition of the error signal and application of a different convergence factor for each band are derived. With this approach, tracking ability and performance in steady state can be traded off along the frequency domain giving rise to estimates of the adaptive filter coefficients closer to the ideal response as compared to those obtained with conventional least-mean-square (LMS) and recursive least-squares (RLS) algorithms, particularly when the statistical properties of the analyzed signal vary along the frequency spectrum. A new adaptation technique for the forgetting factor depending exclusively on the autocorrelation values of the input signal is also introduced and a multi-band RLS algorithm, with an independent variable forgetting factor for each band, suitable for the analysis of nonstationary signals is described. Computer experiments comparing the performance of multi-band and conventional LMS and RLS algorithms are shown View full abstract»

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  • Design and implementation of bandpass delta-sigma modulators using half-delay integrators

    Page(s): 535 - 546
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    Two bandpass delta-sigma A/D converters using half delay, integrators have been designed and implemented in a 2-μm n-well double-poly double-metal CMOS process. The first design, a fourth-order architecture with an input modulation network, achieves a signal-to-noise ratio (SNR) of 73 dB over a 0.005π input bandwidth, while the second design, a sixth-order topology, yielded a measured SNR of 80 dB over a 0.004π input bandwidth View full abstract»

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  • Dynamic bit allocation in video combining for multipoint conferencing

    Page(s): 644 - 648
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    For multipoint video conferencing over a wide-area network, a video bridge is often used to combine the coded video signals from multiple participants into a single video for display. The video combining can be done in the coded-domain by concatenating coded video bitstreams, or in the pixel-domain by transcoding. In this paper we compare the video quality using the two approaches for a multipoint video conference over a symmetrical wide-area network such as Integrated Service Digital Network (ISDN). We observe that in most multipoint video conferences usually only one or two persons are active at one time, while other participants are just listening with little motion. To achieve similar video quality for all the conference participants, the active persons require higher bit rates than the inactive persons. By doing video combining using the transcoding approach and dynamically allocating more bits to the active persons, we show that the achieved video quality can be much better than that can be achieved using the coded-domain video combining approach View full abstract»

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  • A 160-MHz fourth-order double-sampled SC bandpass sigma-delta modulator

    Page(s): 547 - 555
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    A fully differential double-sampled switched-capacitor (SC) architecture for a fourth-order bandpass ΣΔ modulator is presented. This architecture is based on a double-sampled SC delay circuit. The effect of opamp nonidealities (finite dc gain and nonzero input capacitance) on the notch frequency of this modulator is analyzed. The modulator is implemented in a 0.5-μm CMOS technology and operates at a clock frequency of 80 MHz, making the effective sampling rate 160 MHz. The image signal is about 40 dB below the fundamental signal. The measured signal-to-noise-plus-distortion (SNDR) is 47 dB (not including the image) over a 1.25-MHz bandwidth centered at 40 MHz. The circuit operates at 3 V and consumes 65 mW View full abstract»

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  • On-chip voltage down converter for low-power digital system

    Page(s): 617 - 625
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    An on-chip differential-amplifier-based DC-to-DC voltage down converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator and high current drive capability. VDC converts 5 V to lower voltage so that the internal circuits of the chip are used. In this paper, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA) and temperature dependency of 3.2 mV/°C. The VDC chip was fabricated in a 0.8 μm single-poly-double-metal CMOS process and layout size is 690×210 μm2. The output voltage is stabilized within ±2.8% for supply voltage with ±10% variation achieved View full abstract»

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  • Steiner tree constructions in λ3-metric

    Page(s): 563 - 574
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    We consider Steiner minimal trees (SMT's) in metrics defined by given orientations. The problem is motivated by wiring considerations of VLSI chips when the wiring direction is not restricted to only horizontal and vertical. In particular, we concentrate on the case when the given orientations form angles of 0°, 60°, and 120° (λ3-metric) since many interesting results can be obtained which may shed light on other metrics in the family. Specifically, we show that any SMT can be transformed to one with their Steiner points located on the grid points of a multilevel grid, where the number of levels can be quite small. Based on this result, we have developed a simulated annealing-based algorithm to generate near-optimal SMT's. Empirical results and comparisons with Euclidean cases are also given View full abstract»

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  • A comb filter design using fractional-sample delay

    Page(s): 649 - 653
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    In this paper, a new comb filter design method using fractional sample delay is presented. First, the specification of the comb filter design is transformed into that of fractional delay filter design. Then, conventional finite impulse response (FIR) and allpass filter design techniques are directly applied to design fractional delay filter with transformed specification. Next, we develop a constrained fractional delay filter design approach to improve the performance of the direct design method. Finally, several design examples and an experiment of power line interference removal in an electrocardiogram (ECG) signal is demonstrated to illustrate the effectiveness of this new design approach View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope