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Solid-State Circuits, IEEE Journal of

Issue 5 • Date May 1998

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Displaying Results 1 - 19 of 19
  • A reduced clock-swing flip-flop (RCSFF) for 63% power reduction

    Page(s): 807 - 811
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop which embodies the leakage current cutoff mechanism. The RCSFF can reduce the clock system power of a VLSI down to one-third compared to the conventional flip-flop. This power improvement is achieved through the reduced clock swing down to 1 V. The area and the delay of the RCSFF can also be reduced by a factor of about 20% compared to the conventional flip-flop. The RCSFF can also reduce the RC delay of a long RC interconnect to one-half View full abstract»

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  • High-performance microprocessor design

    Page(s): 676 - 686
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    Three generations of Alpha microprocessors have been designed using a proven custom design methodology. The performance of these microprocessors was optimized by focusing on high-frequency design. The Alpha instruction set architecture facilitates high clock speed, and the chip organization for each generation was carefully chosen to meet critical paths. Digital has developed six generations of CMOS technology optimized for high-frequency design. Complex circuit styles were used extensively to meet aggressive cycle time goals. CAD tools were developed internally to support these designs. This paper discusses some of the technologies that have enabled Alpha microprocessors to achieve high performance View full abstract»

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  • A 2-V 1.9-GHz Si down-conversion mixer with an LC phase shifter

    Page(s): 812 - 815
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    This paper describes a 2.0-V 1.9-GHz silicon down-conversion mixer with an LC phase shifter in a 20-GHz bipolar process. In this circuit, the lower emitter-coupled pair in a Gilbert cell mixer is removed to enable low voltage operation, and instead an LC phase shifter is inserted between two current sources. The time constant of the LC phase shifter has to be optimized, because the phase shifter acts as a low-pass filter and the lower cutoff frequency results in the loss of signal power. By this optimization, it can keep both high conversion gain and low distortion. The experimental results show conversion gain of 7.0 dB and the input third-order intercept point of -1.0 dBm are realized at 2.0 V View full abstract»

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  • 1.04 GBd low EMI digital video interface system using small swing serial link technique

    Page(s): 816 - 823
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd View full abstract»

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  • Issue logic for a 600-MHz out-of-order execution microprocessor

    Page(s): 707 - 712
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    The logic and circuits are presented for a 20-entry instruction queue which scoreboards 80 registers and issues four instructions per cycle in a 600-MHz microprocessor. The request logic and arbiter circuits that control integer execution are described in addition to a novel compaction scheme that maintains temporal order in the queue. The issue logic data path is implemented in 141000 transistors, occupying 10 mm2 in a 0.35-μm CMOS process View full abstract»

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  • A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme

    Page(s): 779 - 786
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    A prototype 1 Gbit synchronous DRAM with independent subarray-controlled isolation and hierarchical decoding schemes is demonstrated to alleviate the difficulties encountered in high-density devices with regard to failure analysis and performance optimization. The scheme to isolate memory arrays from “hard” defects and to overcome the dc leakages of “soft” defects with external sources allows monitoring of the leakage current for the defect analysis and testing of the device without being limited by the capabilities of on-chip voltage sources. A hierarchical decoding scheme with a dynamic CMOS series logic predecoder achieves improvements in circuit speed, power, and complexity. As a result, evaluation of the prototype devices can be facilitated, and the optimized circuit schemes achieve enhanced circuit performance. A fully working 1 Gbit synchronous DRAM with a chip size of 570 mm2 was fabricated using a 0.16 μm CMOS process and tested for excellent functionality up to 143 MHz View full abstract»

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  • A 32×32-b adiabatic register file with supply clock generator

    Page(s): 696 - 701
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    A 32×32-b adiabatic register file with one read port and one write port is designed. A four-phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the word line and bit line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are based on efficient charge recovery logic (ECRL) and are integrated using 0.8 μm complimentary metal-oxide-semiconductor (CMOS) technology. Measurement results show that power consumption of the core is significantly reduced by a factor of up to 3.5 compared with a conventional circuit View full abstract»

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  • 400-MHz random column operating SDRAM techniques with self-skew compensation

    Page(s): 770 - 778
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    High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAM's. First, a self-skew compensating technique enables 400-Mbit/s address and data detection. Second, a novel trihierarchical WL scheme realizes multibank operation without access or area penalties. Third, an interleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz×32 DDR operation, namely, 1.6-Gbyte/s data rate operation, has been confirmed View full abstract»

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  • A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs]

    Page(s): 753 - 761
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    A DS-CDMA demodulator uses analog sampled-data signal processing to achieve a 75-mW power dissipation and a 128-MS/s processing rate in a 1.2-μm double-metal double-poly CMOS process. To demodulate the signal, a low-power passive correlation technique is introduced that eliminates the integrating opamp with its associated power and settling time overhead. In a prototype demodulator, six 64-chip correlators recover the 2-Mb/s data stream from the doubly modulated [pseudorandom noise (PN) and Walsh] quadrature input signal. An on-chip 10-b pipelined ADC sampling at 8 MS/s follows the analog correlation to permit digital implementation of the acquisition and tracking algorithms View full abstract»

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  • A multimode digital detector readout for solid-state medical imaging detectors

    Page(s): 733 - 742
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A multipurpose digital detector readout for medical imaging applications is presented. The readout is capable of measuring both current and charge, allowing a single detector array to perform imaging functions previously accomplished with two separate machines. The circuit employs a variable rate ΣΔ analog-to-digital converter (ADC) to measure current over a 130-dB dynamic range in a 1 kHz band and resolve charge pulses down to 360 e- at 100 000 events/s. Detector currents of up to 7 μA and charge pulses as large as 25 fC can be measured. A low-noise charge sensing amplifier (CSA) is combined with digital pulse shaping to optimize the noise performance and flexibility of the charge measurements. Fabricated in an 1.2 μm complimentary metal-oxide-semiconductor (CMOS), the circuit occupies 1.5 mm2 and dissipates 11 mW/channel from a 5 V supply View full abstract»

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  • A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

    Page(s): 793 - 799
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    This paper proposes and reports a low-power SRAM using a charge-transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier overcomes the Vth relative difference between the pair MOS transistors, and thus reduces the input offset voltage. The encoded-bus scheme reduces the number of signals being switched to cut the capacitive load. These read-path dynamic circuits have eight-timings which a low-power DLL produces. The fabricated 0.35-μm-rule 2k-by-16-bit SRAM operated at 50 MHz with the power dissipation of 5 mW at 1 V View full abstract»

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  • CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters

    Page(s): 762 - 769
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved View full abstract»

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  • A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling

    Page(s): 713 - 722
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-μm HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3× the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10-14 View full abstract»

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  • A data-transition look-ahead DFF circuit for statistical reduction in power consumption

    Page(s): 702 - 706
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    A new data-transition look-ahead DFF (DL-DFF) that reduces the power consumption of CMOS LSI's is proposed. The power consumption is reduced in accordance with the data-transition probability. The main feature of the DL-DFF is that the clock signal is deactivated when there are no data transitions. This reduces the power consumption when the data-transition probability is low. The power consumption of a DL-DFF is compared to that of a conventional one by measuring a test chip fabricated using a 0.25-μm CMOS/SIMOX process. It is found that a DL-DFF consumes less power than a conventional one when the data-transition probability is under 60%. For example, when the data-transition probability is 25%, it consumes 29% less power. Moreover, some suitable applications of a DL-DFF are presented View full abstract»

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  • Self-powered signal processing using vibration-based power generation

    Page(s): 687 - 695
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    Low power design trends raise the possibility of using ambient energy to power future digital systems. A chip has been designed and tested to demonstrate the feasibility of operating a digital system from power generated by vibrations in its environment. A moving coil electromagnetic transducer was used as a power generator. Calculations show that power on the order of 400 μW can be generated. The test chip integrates an ultra-low power controller to regulate the generator voltage using delay feedback techniques, and a low power subband filter DSP load circuit. Tests verify 500 kHz self-powered operation of the subband filter, a level of performance suitable for sensor applications. The entire system, including the DSP load, consumes 18 μW of power. The chip is implemented in a standard 0.8 μm CMOS process. A single generator excitation produced 23 ms of valid DSP operation at a 500 kHz clock frequency, corresponding to 11,700 cycles View full abstract»

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  • A 950-MHz IF second-order integrated LC bandpass delta-sigma modulator

    Page(s): 723 - 732
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A second-order integrated LC bandpass delta-sigma modulator is presented. This modulator is implemented in a 0.5-μm bipolar process and can be used for digitizing radio frequency or high intermediate frequency signals. It employs an integrated LC resonator with active Q-enhancement and two nonreturn-to-zero digital-to-analog pulse-shaping feedback loops. The modulator test chip achieves a signal-to-noise ratio of 57 dB over a 200-kHz bandwidth for converting a 950-MHz signal, and dissipates 135 mW with a 5-V supply View full abstract»

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  • On-chip spiral inductors with patterned ground shields for Si-based RF ICs

    Page(s): 743 - 752
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor View full abstract»

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  • An access-sequence control scheme to enhance random-access performance of embedded DRAM's

    Page(s): 800 - 806
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    An embedded DRAM enables a high data-transfer rate since it provides an on-chip wide-bus interconnection. However, the net data-transfer rate is reduced by page misses because of the inherently large row-access time of DRAM's. We previously proposed a multibank DRAM macro based on a micromodule architecture to overcome this problem. The pipelined access of the DRAM macro is especially useful for regular access in graphics applications. In this paper, we propose an access-sequence control scheme which enhances the random-access performance of embedded DRAMs. Access ID numbers, an access queue register, and a write-data buffer combined with the multibank DRAM enable out-of-sequence access which reduces the page-miss penalty during random access. In the case of four successive accesses, the estimated total access time was, respectively, reduced by up to 38 and 32% for one and two page misses, and for five successive accesses with one or two page misses, it was, respectively, reduced by up to 44 and 45% View full abstract»

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  • High-density chain ferroelectric random access memory (chain FRAM)

    Page(s): 787 - 792
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    A new chain ferroelectric random access memory-a chain FRAM-has been proposed. A memory cell consists of parallel connection of one transistor and one ferroelectric capacitor, and one memory cell block consists of plural memory cells connected in series and a block selecting transistor. This configuration realizes the smallest 4 F2 size memory cell using the planar transistor so far reported, and random access. The chip size of the proposed chain FRAM can be reduced to 63% of that of the conventional FRAM when 16 cells are connected in series. The fast nondriven half-Vdd cell-plate scheme, as well as the driven cell-plate scheme, are applicable to the chain FRAM without polarization switching during the standby cycle thanks to short-circuiting ferroelectric capacitors. It results in fast access time of 45 ns and cycle time of 70 ns without refresh operation View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan