By Topic

Electron Devices, IEEE Transactions on

Issue 5 • Date May 1998

Filter Results

Displaying Results 1 - 23 of 23
  • Suspended SOI structure for advanced 0.1-μm CMOS RF devices

    Page(s): 1039 - 1046
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (224 KB)  

    Modern silicon-on-insulator (SOI) technology and 0.1-μm-channel-length complementary metal oxide silicon (CMOS) devices make it possible to fabricate high-performance RF devices by using standard Si ULSI processes. Using the buried oxide layer of an SOI wafer as an etching stopper, we were able to integrate a suspended inductor, with high-inductor resonance-frequency of 19.6 GHz, and high-performance 0.1-μm CMOS devices. Moreover, we experimentally show that this suspended CMOS has acceptable short-channel immunity. Using two-dimensional (2-D) simulation, we clarify that the gate-potential spread sufficiently suppresses the potential shifts, which results in good short-channel characteristics View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Monitoring hot-carrier degradation in SOI MOSFETs by hot-carrier luminescence techniques

    Page(s): 1135 - 1139
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    This paper addresses the problem of hot-carrier degradation and lifetime monitoring in SOI MOSFETs by means of hot-carrier-induced luminescence measurements. The peculiar emission behavior of SOI devices is clarified over a broad range of bias conditions by means of comparison with that of BULK MOSFETs. It is shown that detailed analysis of hot-carrier luminescence measurements at different photon energies provides a noninvasive monitoring tool for various aspects of degradation, such as worst case bias conditions, threshold voltage shift, and variations of the electric field and hot-carrier population in the damaged region. The measured light intensity represents also a sensitive acceleration factor for the extrapolation of lifetimes to real operating conditions View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Body-contacted SOI MOSFET structure and its application to DRAM

    Page(s): 1063 - 1070
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A body-contacted (BC) SOI MOSFET structure without the floating-body effect is proposed and successfully demonstrated. The key idea of the proposed structure is that the field oxide does not consume the silicon film on buried oxide completely, so that the well contact can suppress the body potential increase in SOI MOSFET through the remaining silicon film between the field oxide and buried oxide. The junction capacitance of the proposed structure which ensures high-speed operation can also maintain that of the conventional thin-film SOI MOSFET at about 0.5 V. The measured device characteristics show the suppressed floating-body effect as expected. A 64 Mb SOI DRAM chip with the proposed BC-SOI structure has been also fabricated successfully. As compared with bulk MOSFET's, the proposed SOI MOSFET's have a unique degradation-rate coefficient that increases with increasing stress voltage and have better ESD susceptibility. In addition, it should be noted that the proposed SOI MOSFET's have a fully bulk CMOS compatible layout and process View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Impact of scaling silicon film thickness and channel width on SOI MOSFET with reoxidized MESA isolation

    Page(s): 1105 - 1110
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    The characteristics of reoxidized MESA isolation for silicon-on-insulator (SOI) MOSFET have been studied in terms of the dependence of device performance on silicon film thickness and channel width scaling. For devices with silicon film thickness (TSi) smaller than a critical thickness, humps appear in subthreshold IV and negative threshold voltage shift is observed in narrow width devices. The width encroachment (ΔW) also increases rapidly with reducing T Si. These observations can be explained by the formation of sharp beak and accelerated sidewall oxide growth in these devices. A simple guideline is given to optimize the reoxidation process for different TSi View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design issues and insights for low-voltage high-density SOI DRAM

    Page(s): 1055 - 1062
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    A physics-based study of floating-body effects on the operation of SOI DRAM is described. The study, which is based on device and circuit simulations using a physical SOI MOSFET model calibrated to an actual partially-depleted (PD) SOI DRAM technology, addresses the performance of the peripheral circuitry, e.g., the sense amplifier, as well as the dynamic retention of the data storage cell. Design insight for low-voltage high-density SOI DRAM is attained. Double cell design is shown to yield a dynamic retention time long enough for gigabit memories, and crude body-source ties for nMOS, with pMOS bodies floating, are shown to effectively suppress instabilities in the sense amplifier View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Suppression of parasitic bipolar action in ultra-thin-film fully-depleted CMOS/SIMOX devices by Ar-ion implantation into source/drain regions

    Page(s): 1071 - 1076
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    This paper proposes a new technique that can effectively suppress the parasitic bipolar action (PBA) in ultrathin-film fully-depleted (FD)nMOSFET's/SIMOX with a floating body. In this technique, recombination centers are created in the source and drain (S/D) regions by deep Ar-ion implantation. They act to reduce the number of holes that accumulate in the body region by increasing the hole current flowing from the body region into the source region. Consequently, the rise of the body potential is lowered, and the parasitic bipolar action can be suppressed. A 0.25-μm gate nMOSFET/SIMOX fabricated with an Ar dose of 2×1014 cm-2 exhibited excellent improvements in electrical characteristics: a reduction in the off-leakage current of over two orders of magnitude and an increase in the drain-to-source breakdown voltage beyond 0.6 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Opposite-channel-based injection of hot-carriers in SOI MOSFET's: physics and applications

    Page(s): 1147 - 1154
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    An extensive study of the recently observed opposite-channel-based injection (OCBI) of hot-carriers in SOI MOSFET's is carried out by PISCES numerical calculations. The study reveals similar patterns of injection for partially-depleted (PD) and fully-depleted (FD) devices, although there are significant quantitative differences. Important differences also exist when stressing the device with the body floating versus body grounded. The results demonstrate that when stressing one channel, carriers can and are injected into the opposite gate. The results also demonstrate that under appropriate bias conditions pure electron/hole injection takes place, and establish these conditions. The practical significance of this ability to inject only electrons or only holes in any desired sequence is illustrated by exploiting it to investigate the time-power law of interface state generation and to design a SOI EEPROM cell with a back channel based erasing scheme View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling

    Page(s): 1017 - 1025
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (320 KB)  

    The maturation of low-cost silicon-on-insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs. The extracted model is shown to be valid up to 40 GHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Hot-carrier effects and lifetime prediction in off-state operation of deep submicron SOI N-MOSFETs

    Page(s): 1140 - 1146
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Hot-carrier effects (HCE) induced by the parasitic bipolar transistor (PBT) action are thoroughly investigated in deep submicron N-channel SOI MOSFETs for a wide range of temperature and gate length. A multistage device degradation is highlighted for all the experimental conditions. Original Vt variations are also obtained for short-channel devices, a reduction of the threshold voltage being observed for intermediate values of stress time in the case of high stress drain biases. At low temperature (LT), an improvement of the device aging can be obtained in the low Vd range because of the significant reduction of the leakage current in the PBT regime. However, in the case of high Vd, since the strong leakage current cannot be suppressed at LT, the device aging is larger than that obtained at room temperature. On the other hand, the device lifetime in off-state operation is carefully predicted as a function of gate length with various methods. Numerical simulations are also used in order to propose optimized silicon-on-insulator (SOI) architectures for alleviating the PBT action and improving the device performance and reliability View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of collector structure on the FBSOA of the dielectrically-isolated LIGBT

    Page(s): 1155 - 1161
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    In this paper, the dependence of the forward biased safe operating area (FBSOA) on the collector structures of the dielectrically-isolated (DI) lateral insulated gate bipolar transistor (LIGBT) has been analyzed. In addition to the on-state and switching characteristics, pulsed measurements were performed to determine the FBSOA of these devices. Two-dimensional (2-D) numerical simulations were performed to understand the physics behind the operation of devices fabricated with various collector designs. These studies reveal that some of the structures behave like the conventional LIGBT, while others behave like the LDMOSFET with respect to their FBSOA. Some of the structures also exhibit a unique high-voltage blocking ability while carrying current, while having much smaller breakdown voltages View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced thin-film silicon-on-sapphire technology: microwave circuit applications

    Page(s): 1047 - 1054
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    This paper reviews the prospects of thin-film silicon-on-sapphire (TFSOS) CMOS technology in microwave applications in the 1-5 GHz regime and beyond and presents the first demonstration of microwave integrated circuits based on this technology, MOSFET's optimized for microwave use, with 0.5-μm optically defined gate lengths and a T-gate structure, have ft values of 25 GHz (14 GHz) and fmax values of 66 GHz (41 GHz) for n-channel (p-channel) devices and have noise figure values below 1 db at 2 GHz, some of the best reported performance characteristics of any silicon-based MOSFET's to date. On-chip spiral inductors exhibit quality factors above ten. Circuit performance compares favorably with that of other CMOS-based technologies and approach performance levels similar to those obtained by silicon bipolar technologies. The results demonstrate the significant potential of this technology for microwave applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • BESS: a source structure that fully suppresses the floating body effects in SOI CMOSFETs

    Page(s): 1077 - 1083
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (256 KB)  

    The most serious problem preventing the widespread use of SOI CMOSFETs-the floating body effects-are almost fully suppressed by a new source structure. In an nMOSFET, this new structure can be represented by an equivalent circuit of a bipolar embedded source structure (BESS) just beneath the n+ source junction. In the source region, or p type (or n--type) recombination centers are embedded in a low-impurity-diffusion region (the base) and acts as a collector of the excess body carriers. The low-impurity-source region lowers the diffusion potential barrier for holes at the source junction. The solid-phase epitaxial regrowth mechanism of the Si+ implanted amorphous SOI layer was studied and applied to fabricate a prototype of this device capable of symmetric source-drain operations with the same source-drain breakdown voltage as that of a bulk device View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Approaches to extra low voltage DRAM operation by SOI-DRAM

    Page(s): 1000 - 1009
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (404 KB)  

    The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-μm 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-current small-parasitic-capacitance MOSFET on a poly-Si interlayered (PSI:Ψ) SOI wafer

    Page(s): 1111 - 1115
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    A new type of silicon-on insulator (SOI) structure has been fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si and SiO2. A device with an ideal epitaxial channel structure was fabricated using a conventional MOS process on this novel multilayered SOI (100-nm SOI/10-nm SiO2/poly-Si/500-nm SiO2) wafer. In this device, the highly concentrated p+ poly-Si just beneath the nMOS channel region acts as a punchthrough stopper, and the buried thin backgate oxide under the SOI layer acts as an impurity diffusion barrier, keeping the impurity concentration in the SOI film at its original low level. The device fabricated was an ultrathin SOI MOSFET capable of operating at a current 1.5 times that of conventional hundred-nm devices at low voltages View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Three mechanisms determining short-channel effects in fully-depleted SOI MOSFETs

    Page(s): 1116 - 1121
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    Mechanisms determining short-channel effects (SCE) in fully-depleted (FD) SOI MOSFETs are clarified based on experimental results of threshold voltage (VT) dependence upon gate length, and analysis using a two-dimensional (2-D) device simulator. Drain-induced barrier lowering (DIBL) effect is a well known mechanism which determines the SCE in conventional bulk MOSFETs. In FDMOSFETs, two more peculiar and important mechanisms are found out, i.e., the accumulation of majority carriers in the body region generated by impact ionization, and the DIBL effect on the barrier height for majority carriers at the edge of the source near the bottom of the body. Due to these peculiar mechanisms, VT dependence upon gate length in the short-channel region is weakened. It is also shown that floating body effects, the scatter of VT, and transient phenomena are suppressed due to the SCE peculiar to FD MOSFETs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Monte Carlo simulation of electron transport properties in extremely thin SOI MOSFET's

    Page(s): 1122 - 1126
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    Electron mobility in extremely thin-film silicon-on-insulator (SOI) MOSFET's has been simulated. A quantum mechanical calculation is implemented to evaluate the spatial and energy distribution of the electrons. Once the electron distribution is known, the effect of a drift electric field parallel to the Si-SiO2 interfaces is considered. The Boltzmann transport equation is solved by the Monte Carlo method. The contribution of phonon, surface-roughness at both interfaces, and Coulomb scattering has been considered. The mobility decrease that appears experimentally in devices with a silicon film thickness under 20 nm is satisfactorily explained by an increase in phonon scattering as a consequence of the greater confinement of the electrons in the silicon film View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Noise contribution of the body resistance in partially-depleted SOI MOSFETs

    Page(s): 1033 - 1038
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB)  

    An additional noise component is observed in the noise spectrum of transistors in a partially-depleted (PD) medium-thickness SOI-CMOS technology. We identify the origin of this additional noise in the noisy resistance of the body film. This resistance, coupled to the gate capacitance, forms an RC filter and generates the hump-shape of the additional noise component. Several experimental observations that support this model are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Fully-depleted SOI CMOS for analog applications

    Page(s): 1010 - 1016
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    Fully-depleted (FD) SOI MOSFETs offer near-ideal properties for analog applications. In particular their high transconductance to drain current ratio allows one to obtain a higher gain than from bulk devices, and the reduced body effect permits one to fabricate more efficient pass gates. The excellent behavior of SOI MOSFETs at high temperature or at gigahertz frequencies is outlined as well View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Advanced technologies for optimized sub-quarter-micrometer SOI CMOS devices

    Page(s): 1092 - 1098
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    Two manufacturable technologies of fully-depleted (FD) thin-film silicon-on-insulator (SOI) MOSFET's for low-power applications are proposed in this paper. To maintain high current drive while aggressively thinning down the SOI film, silicide is to be formed on Ge-damaged silicon layers. Ge preamorphization facilitates silicide formation at low temperature (~450°C) and effectively controls the silicide depth without void formation. It also reduces the floating body effect. In addition, a reliable gate work-function engineering is introduced for good threshold voltage management. A p+SiGe/Si stack gate alleviates the threshold voltage instability of SOI due to film thickness nonuniformity and broadens the design window for channel doping. These advanced technologies, compatible with existing bulk CMOS technology, are integrated into SOI CMOS process. Excellent electrical device results are presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thin silicide development for fully-depleted SOI CMOS technology

    Page(s): 1099 - 1104
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10-7Ω-cm 2 is necessary for achieving low contact resistance in a sub-0.25-μm fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Semiconductor thickness effects in the double-gate SOI MOSFET

    Page(s): 1127 - 1134
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    Influence of the semiconductor film thickness in the double-gate silicon on-insulator (SOI) MOSFET on the electron concentration distribution, electron charge density, threshold voltage, electron effective mobility, and drain current is theoretically analyzed. The consideration of the semiconductor region is based on two descriptions: the “classical” model based on a solution to the Poisson equation and the “quantum” model based on a self-consistent solution to the Schrodinger and Poisson equation system. The electron effective mobility and the drain current are calculated with the use of the local mobility model View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • SOI MOSFET with buried body strap by wafer bonding

    Page(s): 1084 - 1091
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    Although the buried oxide in the silicon-on-insulator (SOI) MOSFET makes possible higher performance circuits, it is also responsible for various floating body effects, including the kink effect, drain current transients, and history dependence of output characteristics. It is difficult to incorporate an effective contact to the body because of limitations imposed by the SOI structure. One candidate, which maintains device symmetry, is the lateral body contact. However, high lateral body resistance makes the contact effective only in narrow width devices. In this work, a buried lateral body contact in SOI is described which consists of a low-resistance polysilicon strap running under the MOSFET body along the device width. MOSFET's with effective channel length of 0.17 μm have been fabricated incorporating this buried body strap, showing improved breakdown characteristics. Low leakage of the source and drain junctions demonstrates that the buried strap is compatible with deep submicron devices. Device modeling and analysis are used to quantify the effect of strap resistance on device performance. By accounting for the lateral resistance of the body, the model can be used to determine the maximum allowable device width, given the requirement of maintaining an adequate body contact View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling of SOI-MOS capacitors C-V behavior: partially- and fully-depleted cases

    Page(s): 1026 - 1032
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    A model is presented for the C-V characteristics of partially-depleted (PD) and fully-depleted (FD) SOI-MOS capacitors. The proposed model is flexible, allowing introduction of all types of nonidealities typical to MOS type structures. New formulae for the low- and high-frequency capacitances of these structures are derived. Due to the various charges stored in these structures, unusual and more complex C-V curves are obtained. C-V curves where interface-state densities have been individually introduced (one at a time) at all three SiO2-Si interfaces of the SOI-MOS-C are also demonstrated. The model has been validated by fitting the predicted HF C-V curves for SOI-MOS-C and its inherent structure, the SIS capacitor, to the experimental data. The extracted electrophysical parameters of the studied structures, for both PD and FD cases, are very close, if not the same as the values determined during their fabrication View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology