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Computers, IEEE Transactions on

Issue 2 • Date Feb 1998

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Displaying Results 1 - 18 of 18
  • A parallel algorithm for state assignment of finite state machines

    Publication Year: 1998 , Page(s): 242 - 246
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    Optimization of large sequential circuits has become unmanageable in CAD of VLSI due to time and memory requirements. We report a parallel algorithm for the state assignment problem for finite state machines. Our algorithm has three significant contributions: it is an asynchronous parallel algorithm portable across different MIMD machines; time and memory requirements reduce linearly with the number of processors, enabling the parallel implementation to handle large problem sizes; and the quality of the results for multiprocessor runs remains comparable to the serial algorithm on which it is based due to an implicit backtrack correction mechanism built into the parallel implementation View full abstract»

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  • ATPG for heat dissipation minimization during test application

    Publication Year: 1998 , Page(s): 256 - 262
    Cited by:  Papers (86)  |  Patents (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    A automatic test pattern generator (ATPG) algorithm is proposed that reduces switching activity (between successive test vectors) during test application. The main objective is to permit safe and inexpensive testing of low power circuits and bare die that might otherwise require expensive heat removal equipment for testing at high speeds, Three new cost functions, namely transition controllability, observability, and test generation costs, have been defined. It has been shown, for a fanout free circuit under test, that the transition test generation cost for a fault is the minimum number of transitions required to test a given stuck-at fault. The proposed algorithm has been implemented and the generated tests are compared with those generated by a standard PODEM implementation for the larger ISCAS85 benchmark circuits. The results clearly demonstrate that the tests generated using the proposed ATPG can decrease the average number of (weighted) transitions between successive test vectors by a factor of 2 to 23 View full abstract»

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  • A reliable fail-safe system

    Publication Year: 1998 , Page(s): 236 - 241
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (272 KB)  

    The paper describes a fault tolerant system that is based on two replicas of a self checking module and on an error masking interface. The main contributions of this work rely on the fail safe/strongly fail safe design of the error masking interface, and on the analysis of the competitiveness of this fault tolerant scheme with respect to its reliability View full abstract»

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  • On the complexity of designing optimal branch-and-combine clock networks

    Publication Year: 1998 , Page(s): 264 - 269
    Cited by:  Papers (2)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    Recently, an unconventional clock distribution scheme, called Branch-and-Combine (BaC) was proposed. The scheme is the first to guarantee constant skew upper bound irrespective of the clocked network's size. In BaC clocking, a set of interconnected nodes perform simple processing on clock signals such that the path from the source to any node is automatically and adaptively selected such that it is the shortest delay path. The graph underlying a BaC network is constrained by the requirement that each pair of adjacent nodes is in a cycle of length ⩽k, where k is the feature cycle length. The graph representing such a network is called a BaC(k) graph. The feature cycle length (k) is an important parameter upon which skew bound and node function depend. We study the complexity of the general problem of designing a minimum cost BaC network for clocking a data processing network of arbitrary topology so that a certain feature cycle length is satisfied. We define two versions of the problem, differing in the way we are allowed to place edges in the graph representing the BaC network. We show that, in both cases, the general optimization problem is NP hard. We also provide efficient heuristic algorithms for both versions of the optimization problem. When k=2, the two versions of the optimization problem become the same and can be solved in polynomial time. For k=3, the complexity is still unknown View full abstract»

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  • A learning multiple-valued logic network: algebra, algorithm, and applications

    Publication Year: 1998 , Page(s): 247 - 251
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    We propose a multiple valued logic (MVL) network with functional completeness and develop its learning capability. The MVL network consists of layered arithmetic piecewise linear processors. Since the arithmetic operations of the network are basically a wired sum and a piecewise linear operation, their implementations should be rather simple and straightforward. Furthermore, the MVL network can be trained by the traditional backpropagation algorithm directly. The algorithm trains the networks using examples and appears to be available for most MVL problems of interest View full abstract»

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  • A note on the complexity of Dijkstra's algorithm for graphs with weighted vertices

    Publication Year: 1998
    Cited by:  Papers (40)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (72 KB)  

    Let G(V, E) be a directed graph in which each vertex has a nonnegative weight. The cost of a path between two vertices in G is the sum of the weights of the vertices on that path. We show that, for such graphs, the time complexity of Dijkstra's algorithm (E.W. Dijkstra, 1959), implemented with a binary heap, is O(|E|+|V|log|V|) View full abstract»

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  • Efficient multiplier architectures for Galois fields GF(24n )

    Publication Year: 1998 , Page(s): 162 - 170
    Cited by:  Papers (23)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    This contribution introduces a new class of multipliers for finite fields GF((2n)4). The architecture is based on a modified version of the Karatsuba-Ofman algorithm (KOA). By determining optimized field polynomials of degree four, the last stage of the KOA and the module reduction can be combined. This saves computation and area in VLSI implementations. The new algorithm leads to architectures which show a considerably improved gate complexity compared to traditional approaches and reduced delay if compared with KOA-based architectures with separate module reduction. The new multipliers lead to highly modular architectures and are, thus, well suited for VLSI implementations. Three types of field polynomials are introduced and conditions for their existence are established. For the small fields, where n=2,3,...,8, which are of primary technical interest, optimized field polynomials were determined by an exhaustive search. For each field order, exact space and time complexities are provided View full abstract»

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  • Processor saving scheduling policies for multiprocessor systems

    Publication Year: 1998 , Page(s): 178 - 189
    Cited by:  Papers (3)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    In this paper, processor scheduling policies that “save” processors are introduced and studied. In a multiprogrammed parallel system, a “processor saving” scheduling policy purposefully keeps some of the available processors idle in the presence of work to be done. The conditions under which processor saving policies can be more effective than their greedy counterparts, i.e., policies that never leave processors idle in the presence of work to be done, are examined. Sensitivity analysis is performed with respect to application speedup, system size, coefficient of variation of the applications' execution time, variability in the arrival process, and multiclass workloads. Analytical, simulation, and experimental results show that processor saving policies outperform their greedy counterparts under a variety of system and workload characteristics View full abstract»

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  • Computation of √(x/d) in a very high radix combined division/square-root unit with scaling and selection by rounding

    Publication Year: 1998 , Page(s): 152 - 161
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    A very-high radix digit-recurrence algorithm for the operation √(x/d) is developed, with residual scaling and digit selection by rounding. This is an extension of the division and square-root algorithms presented previously, and for which a combined unit was shown to provide a fast execution of these operations. The architecture of a combined unit to execute division, square-root, and √(x/d) is described, with inverse square-root as a special case. A comparison with the corresponding combined division and square-root unit shows a similar cycle time and an increase of one cycle for the extended operation with respect to square-root. To obtain an exactly rounded result for the extended operation a datapath of about 2n bits is needed. An alternative is proposed which requires approximately the same width as for square-root, but produces a result with an error of less than one ulp. The area increase with respect to the division and square root unit should be no greater than 15 percent. Consequently, whenever a very high radix unit for division and square-root seems suitable, it might be profitable to implement the extended unit instead View full abstract»

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  • A new technique for optimization problems in graph theory

    Publication Year: 1998 , Page(s): 190 - 196
    Cited by:  Papers (6)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    This paper presents an efficient technique to map the minimum vertex cover and two closely related problems (maximum independent set and maximum clique) onto the Hopfield neural networks. The proposed approach can be used to find near-optimum solutions for these problems in parallel, and particularly the network algorithm always yields minimal vertex covers. A systematic way of deriving energy functions is described. Based on these relationships, other NP-complete problems in graph theory can also be solved by neural networks. Extensive simulations were performed, and the experimental results show that the network algorithm outperforms the well-known greedy algorithm for vertex cover problems View full abstract»

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  • Analysis of checkpointing schemes with task duplication

    Publication Year: 1998 , Page(s): 222 - 227
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    The paper suggests a technique for analyzing the performance of checkpointing schemes with task duplication. We show how this technique can be used to derive the average execution time of a task and other important parameters related to the performance of checkpointing schemes. The analysis results are used to study and compare the performance of four existing checkpointing schemes. Our comparison results show that, in general, the number of processors used, not the complexity of the scheme, has the most effect on the scheme performance View full abstract»

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  • Floating Steiner trees

    Publication Year: 1998 , Page(s): 197 - 211
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (940 KB)  

    We study the reproducing placement problem, which finds application in layout-driven logic synthesis. In each phase, a module (or gate) is decomposed into two (or more) simpler modules. The goal is to find a “good” placement in each phase. The problem, being iterative in nature, requires an iterative algorithm. In solving the RPP, we introduce the notion of minimum floating Steiner trees (MFST). We employ an MFST algorithm as a central step in solving the RPP. A Hanan-like theorem is established for the MFST problem, and two approximation algorithms are proposed. Experiments on commonly employed benchmarks verify the effectiveness of the proposed technique View full abstract»

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  • Cyclic staggered scheme: a loop allocation policy for DOACROSS loops

    Publication Year: 1998 , Page(s): 251 - 255
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    Within the scope of the multithreaded dataflow, the problem of scheduling/allocation of DOACROSS loops has been discussed and it was shown that the so called staggered allocation offers higher performance and resource utilization than other schemes described in the literature. The staggered scheme, however, produces an unbalanced load among processors. The paper introduces an extension to the staggered scheme-cyclic staggered scheme-that produces a more balanced distribution of iterations among processors. The cyclic staggered scheme is simulated and its performance improvement is analyzed View full abstract»

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  • An approach to designing modular extensible linear arrays for regular algorithms

    Publication Year: 1998 , Page(s): 212 - 216
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    The purpose of this paper is to describe a new method to design unidirectional modular extensible linear arrays for regular algorithms. The time complexity of our method is polynomial and depends only on the number of dimensions of the regular algorithm. The designed linear array is asymptotically optimal in space and time View full abstract»

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  • Solving Boolean equations using ROSOP forms

    Publication Year: 1998 , Page(s): 171 - 177
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (296 KB)  

    Boolean equations are important tools in digital logic. Previous algorithms for solving Boolean equations are based on the Boolean algebra of disjoint SOP forms. In this paper, we develop a new Boolean algebra with more efficient Boolean operation algorithms, called the reduced ordered SOP (ROSOP) forms, which are canonical representations. ROSOPs are closely related to the well-known OBDD data structure. The results here also show the algebraic structure of OBDDs View full abstract»

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  • Destage algorithms for disk arrays with nonvolatile caches

    Publication Year: 1998 , Page(s): 228 - 235
    Cited by:  Papers (11)  |  Patents (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    In a disk array with a nonvolatile write cache, destages from the cache to the disk are performed in the background asynchronously while read requests from the host system are serviced in the foreground. We study a number of algorithms for scheduling destages in a RAID-5 system. We introduce a scheduling algorithm, called linear threshold scheduling, that adaptively varies the rate of destages to disks based on the instantaneous occupancy of the write cache. The performance of the algorithm is compared with that of a number of alternative scheduling approaches, such as least cost scheduling and high/low mark. The algorithms are evaluated in terms of their effectiveness in making destages transparent to the servicing of read requests from the host, disk utilization, and their ability to tolerate bursts in the workload without causing an overflow of the write cache. Our results show that linear threshold scheduling provides the best read performance of all the algorithms compared, while still maintaining a high degree of burst tolerance. An approximate implementation of the linear threshold scheduling algorithm is also described. The approximate algorithm can be implemented with much lower overhead, yet its performance is virtually identical to that of the ideal algorithm View full abstract»

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  • On the polynomial form of Boolean functions: derivations and applications

    Publication Year: 1998 , Page(s): 217 - 221
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    After discussing a few derivations of the canonical, i.e., unique, polynomial form of a Boolean function, various interesting applications of this form are discussed. Mainly, the polynomial form is shown to be very useful for a deeper understanding of switching functions with emphasis on fault tolerant electronics systems View full abstract»

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  • Semi-logarithmic number systems

    Publication Year: 1998 , Page(s): 145 - 151
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    We present a new class of number systems, called Semi-Logarithmic Number Systems, that constitute a family of various compromises between floating-point and logarithmic number systems. This allows trade between the speed of the arithmetic operations and the size of the required tables. We give arithmetic algorithms (addition/subtraction, multiplication, division) for the Semi-Logarithmic Number Systems, and we compare these number systems to the classical floating-point or logarithmic number systems View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org