By Topic

Electron Devices, IEEE Transactions on

Issue 4 • Date Apr 1998

Filter Results

Displaying Results 1 - 25 of 36
  • Simulation and measurement of multiplication in thin-film electroluminescent devices with doped probe layers

    Publication Year: 1998 , Page(s): 768 - 777
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (304 KB)  

    When a single voltage pulse is applied to an electroluminescent (EL) device after previous illumination, the current through the phosphor layer will normally not be homogeneous, but increase from the cathodic side-where the electrons tunnel from-to the anodic side, due to multiplication. The positive charges that remain after the multiplication process cause a positive space charge that has been observed in various experiments and influences the efficiency. In this paper a simple numerical model is proposed for the calculation of charge transfer and light emission, in the case that multiplication takes place during a voltage pulse after previous illumination View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films

    Publication Year: 1998 , Page(s): 912 - 917
    Cited by:  Papers (15)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Qbd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Characterization of highly doped n- and p-type 6H-SiC piezoresistors

    Publication Year: 1998 , Page(s): 785 - 790
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    Highly doped (~2×1019 cm-3) n- and p-type 6H-SiC strain sensing mesa resistors configured in Wheatstone bridge integrated beam transducers were investigated to characterize the piezoresistive and electrical properties. Longitudinal and transverse gauge factors, temperature dependence of resistance, gauge factor (GF), and bridge output voltage were evaluated. For the n-type net doping level of 2×1019 cm-3 the bridge gauge factor was found to be 15 at room temperature and 8 at 250°C. For this doping level, a TCR of -0.24%/°C and -0.74%/°C at 100°C was obtained for the n- and p-type, respectively. At 250°C, the TCR was -0.14%/°C and -0.34%/°C, respectively. In both types, for the given doping level, impurity scattering is implied to be the dominant scattering mechanism. The results from this investigation further strengthen the viability of 6H-SiC as a piezoresistive pressure sensor for high-temperature applications View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 0.1-μm delta-doped MOSFET fabricated with post-low-energy implanting selective epitaxy

    Publication Year: 1998 , Page(s): 809 - 814
    Cited by:  Papers (37)  |  Patents (43)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    A simple fabrication technology for delta-doped MOSFETs, named post-low-energy implanting selective epitaxy (PLISE) is presented. The PLISE technology needs no additional photo-lithography mask, deposition step or etching step even for CMOS devices. The only additional step is growing undoped epitaxial channel layers by UHV-CVD after the channel implantation. With this technology, delta-doped NMOSFETs with 0.1-μm gate length were successfully fabricated. By optimizing the epi-layer thickness and the channel doping level, short-channel effects are suppressed enough to achieve 0.1-μm gate length. Moreover, the junction capacitance at zero bias is reduced by 50% View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Theory of SiGe waveguide avalanche detectors operating at λ=1.3 μm

    Publication Year: 1998 , Page(s): 791 - 796
    Cited by:  Papers (5)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    The potential performance of SiGe waveguide avalanche photodiodes is analyzed for operation at a wavelength of 1.3 μm. It is found that response speeds in excess of 5 Gbit/s with gains of ~40 should be readily achievable in the absence of carrier trapping effects. Analysis of the electron initiated avalanche current shows an initial low-noise fast pulse due to primary ionization. This is followed by a noisy tail involving hole initiated processes. Structures for future experimental study are proposed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A highly efficient 1.9-GHz Si high-power MOS amplifier

    Publication Year: 1998 , Page(s): 953 - 956
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    A 1.9-GHz Si power MOSFET with 50% power-added efficiency and 0.3-1.0 W output power at a 3-5 V supply voltage has been developed for use as a high-power amplifier in cellular telephones. This MOSFET achieves high efficiency and high-power gain at low supply voltage by using a 0.5-μm gate power MOSFET with an Al-shorted metal-silicide/Si gate structure, which improves the cut-off frequency and reduces the on-state resistance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New insights in the relation between electron trap generation and the statistical properties of oxide breakdown

    Publication Year: 1998 , Page(s): 904 - 911
    Cited by:  Papers (233)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    In this paper it is demonstrated in a wide stress field range that breakdown in thin oxide layers occurs as soon as a critical density of neutral electron traps in the oxide is reached. It is proven that this corresponds to a critical hole fluence, since a unique relationship between electron trap generation and hole fluence is found independent of stress field and oxide thickness. In this way literature models relating breakdown to hole fluence or to trap generation are linked. A new model for intrinsic breakdown, based on a percolation concept, is proposed. It is shown that this model can explain the experimentally observed statistical features of the breakdown distribution, such as the increasing spread of the QBD-distribution for ultrathin oxides. An important consequence of this large spread is the strong area dependence of the QBD for ultrathin oxides View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis on accuracy of charge-pumping measurement with gate sawtooth pulses [MOSFETs]

    Publication Year: 1998 , Page(s): 947 - 952
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    Charge-pumping (CP) measurement is performed on MOSFETs with their gates tied to sawtooth pulses. Influence of both rise time (tr) and fall time (tf) on the CP current of the devices with different channel lengths is investigated at different pulse frequencies. Results show that the dominant mechanism affecting the measurement accuracy is the energy range of interface-trap distribution Dit(E) swept by the gate signal for frequencies below 500 kHz and carrier emission for frequencies above 500 kHz. For frequencies higher than 600 kHz, incomplete recombination could be an additional mechanism when tf is too short. Hence, it is suggested that low frequency is more favorable than high frequency, especially for sawtooth pulses with long tr and short tf , due to little carrier emission and negligible geometric effects even for devices as long as 50 μm. However, if high frequency (e.g. 1 MHz) is required to obtain a sufficiently large S/N ratio in the CP current, sawtooth pulses with equal tr and tf should be chosen for the least carrier emission effect and thus more reliable results on interface-state density, Moreover, for both sawtooth and trapezoidal pulses with a typical amplitude of 5 V, a lower limit of 200 ns for tr and tf is necessary to suppress all the undesirable effects in devices shorter than at least 20 μm View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A continuous compact MOSFET model for fully- and partially-depleted SOI devices

    Publication Year: 1998 , Page(s): 821 - 825
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    A fully continuous compact SOI MOSFET model for circuit simulations, that automatically accounts for the for the correct body depletion condition, is presented. Unlike previously reported models that are derived for either fully-depleted (FD) or partially-depleted (PD) devices, our model accounts for the possible transitions between FD and PD behavior during the device operation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance thin-film transistors fabricated using excimer laser processing and grain engineering

    Publication Year: 1998 , Page(s): 925 - 932
    Cited by:  Papers (45)  |  Patents (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    High-performance polysilicon thin-film transistors (TFTs) are fabricated using an excimer laser to recrystallize the undoped channel and dope the source-drain regions. Using a technique we call “grain engineering” we are able to control grain microstructure using laser parameters. Resulting polysilicon films are obtained with average grain sizes of ~4-9×m in sub-100 nm thick polysilicon films without substrate heating during the laser recrystallization process. Using a simple four-mask self-aligned aluminum top-gate structure, we fabricate TFTs in these films. By combining the grain-engineered channel polysilicon regions with laser-doped source-drain regions, TFTs are fabricated with electron mobilities up to 260 cm2/Vs and on/off current ratios greater than 107. To our knowledge, these devices represent the highest performance laser-processed TFTs reported to date fabricated without substrate heating or hydrogenation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Suppressing the parasitic bipolar action in fully-depleted MOSFETs/SIMOX by using back-side bias-temperature treatment

    Publication Year: 1998 , Page(s): 933 - 938
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (128 KB)  

    A new suppression method for parasitic bipolar action is presented for fully-depleted surface-channel nMOSFETs on SIMOX-structures by using the back-side bias-temperature (BSBT) treatment technique. After 10 h of BSBT treatment, increase in source-drain breakdown voltage of about 300 mV was obtained. A peculiar hot-carrier degradation is also suppressed and device lifetime is improved by 20 times. The device characteristics are not degraded by BSBT treatment because it induces a bias stress to back interface between the buried oxide and the active silicon layer, which does not affect the front channel. Influences of BSBT stress to the back interface were investigated using several methods. The suppression mechanism proposed is the generation of charges and interface traps at the back interface View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Accurate cold-test model of helical TWT slow-wave circuits

    Publication Year: 1998 , Page(s): 966 - 971
    Cited by:  Papers (36)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    Recently, a method has been established to accurately calculate cold-test data for helical slow-wave structures using the three-dimensional (3-D) electromagnetic computer code, MAFIA. Cold-test parameters have been calculated for several helical traveling-wave tube (TWT) slow-wave circuits possessing various support rod configurations, and results are presented here showing excellent agreement with experiment. The helical models include tape thickness, dielectric support shapes and material properties consistent with the actual circuits. The cold-test data from this helical model can be used as input into large-signal helical TWT interaction codes making it possible, for the first time, to design a complete TWT via computer simulation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The relation between luminous properties and oxygen content in ZnS:TbOF thin-film electroluminescent devices fabricated by radio-frequency magnetron sputtering method

    Publication Year: 1998 , Page(s): 757 - 762
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    The purpose of this paper is to study the relationship between the oxygen concentration and brightness degradation in ZnS:TbOF green thin-film electroluminescent (EL) devices. The characteristics including crystallinity, optical, and electrical properties were discussed. The brightness-voltage (B-V) measurement results shelved that with higher oxygen-content in ZnS:TbOF phosphor layer, lower brightness was measured. It was consistent with the poor crystallinity, worse photoluminescent intensity, and easier to get moisture in the oxygen-rich (O/Tb>1) phosphor film. Furthermore, deep level transient spectroscopy (DLTS) measurements identified that when the O/Tb ratio was greater than 1, the oxygen-related deep hole traps EH1 and/or EH2 could be detected in the ZnS:TbOF phosphor layer. These E H1 and/or EH2 traps were believed to be the main killers for the brightness of the device since they capture most of the holes from the generated electron-hole pairs. This evidence strongly supports that the modified energy transfer model is more dominant than direct impact excitation during the luminescent process View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-μm CMOS technology

    Publication Year: 1998 , Page(s): 991 - 993
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (92 KB)  

    TCAD tools were used to design and benchmark 0.25-μm buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages VDD>1.4 V, and for NOR gates with V DD>2.4 V View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Full-band Monte Carlo investigation of hot carrier trends in the scaling of metal-oxide-semiconductor field-effect transistors

    Publication Year: 1998 , Page(s): 867 - 876
    Cited by:  Papers (28)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    A full-band Monte Carlo (MC) device simulator has been used to study the effects of device scaling on hot electrons in different types of n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) structures. Simulated devices include a conventional MOSFET with a single source/drain implant, a lightly-doped drain (LDD) MOSFET, a silicon-on-insulator (SOI) MOSFET, and a MOSFET built on an epitaxial layer on top of a heavily-doped ground plane. Different scaling techniques have been applied to the devices, to analyze the effects on the electric field and on the energy distributions of the electrons, as well as on drain, substrate, and gate currents. The results provide a physical basis for understanding the overall behavior of impact ionization and gate oxide injection and how they relate to scaling. The observed nonlocality of transport phenomena and the nontrivial relationship between electric fields and transport parameters indicate that simpler models cannot adequately predict hot carrier behavior at the channel lengths studied (sub-0.3-μm). In addition, our results suggest that below 0.15 μm, the established device configurations (e.g. LDD) that are successful at suppressing the hot carrier population for longer channel lengths, become less useful and their cost-effectiveness for future circuit applications needs to be reevaluated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analytical fully-depleted SOI MOSFET model considering the effects of self-heating and source/drain resistance

    Publication Year: 1998 , Page(s): 797 - 801
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A multicomb variance reduction scheme for Monte Carlo semiconductor simulators

    Publication Year: 1998 , Page(s): 918 - 924
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    We adapt a multicomb variance reduction technique used in neutral particle transport to Monte Carlo micro-electronic device modeling. We implement the method in a two-dimensional (2-D) MOSFET device simulator and demonstrate its effectiveness in the study of hot electron effects. Our simulations show that the statistical variance of hot electrons is significantly reduced with minimal computational cost. The method is efficient, versatile, and easy to implement in existing device simulators View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-performance 670-nm AlGaInP/GaInP visible strained quantum well lasers

    Publication Year: 1998 , Page(s): 763 - 767
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB)  

    We have grown high-performance AlGaInP/GaInP visible (670 mn) strained quantum well lasers by low-pressure metalorganic chemical vapor deposition. With AlInP cladding layer, a high-power AlGaInP/GaInP visible laser diode is achieved. Its threshold current is about 30 mA. The output power of this laser diode can maintain, at least, at 32 mW under continuous-wave (CW) operation at room temperature. High slope efficiency (0.8 mW/mA) and differential quantum efficiency (0.87) can be achieved. To improve beam quality, AlGaInP/GaInP visible lasers with and without depressed index cladding layer are theoretically and experimentally studied. From experimental results, the transverse beam divergence can be reduced from 41.4° to 26.2° while maintaining a low threshold current (from 36 mA to 46 mA). By using the transfer matrix method, our theoretical calculations are in good agreement with the experimental results View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A robust and physical BSIM3 non-quasi-static transient and AC small-signal model for circuit simulation

    Publication Year: 1998 , Page(s): 834 - 841
    Cited by:  Papers (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    A new non-quasi-static (NQS) MOSFET model, which is applicable for both large-signal transient and small-signal ac analysis, has been developed. It employs a physical relaxation time approach to take care of the finite channel charging time to reach equilibrium and the effect of instantaneous channel charge re-distribution. The NQS model is formulated independently from the dc I-V and the charge-capacitor model, thus can be easily applied to any existing simulators. The model has been implemented in the newly released BSIM3 version 3, and comparison has been made among this model, common quasi-static (QS) SPICE models and PISCES two-dimensional (2-D) numerical device simulator. While predicting accurate NQS behavior, the time penalty for using the new model is only about 20-30% more than the common QS models. It is much less than the time required by other NQS models reported. Limitations and compromises between simplicity, efficiency and accuracy are also discussed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of a single-stage depressed collector for high-power, pulsed gyroklystron amplifiers

    Publication Year: 1998 , Page(s): 986 - 990
    Cited by:  Papers (2)  |  Patents (36)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    Net efficiency of microwave devices can be enhanced by recovering energy from the spent electron beam. Depressed collectors are commonly used for low to medium voltage (<100 kV), CW microwave tubes to achieve this objective. Designs of single-stage depressed collectors for high-power, high-voltage, pulsed gyroklystron amplifiers are presented here. Theoretical velocity distributions of the spent beams from 17.14 and 35.0 GHz relativistic gyroklystron designs are used as input to the particle trajectory simulations. The entire spent beam is collected at the cylindrical collector held at a depressed potential with respect to the interaction cavities. The magnetic field profile is adjusted to achieve collection of electrons at the maximum depressed value of the collector potential. A significant improvement in the device efficiency is estimated for both designs. A possible implementation scheme for the energy recovery using a double anode electron gun is described in detail View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Planarized multilevel interconnection using chemical mechanical polishing of selective CVD-Al via plugs

    Publication Year: 1998 , Page(s): 815 - 820
    Cited by:  Papers (2)  |  Patents (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB)  

    A planarization process for selective CVD-Al via plugs using chemical mechanical polishing (CMP) is proposed and a four-level interconnection system with all stacked via plugs is demonstrated. A Cl 2/Ar post-cleaning treatment after Al plug CMP is shown to be the key process in obtaining excellent via chain characteristics with high yield and small resistance scattering. A sandwich of Ti/TiN/Ti barrier layers with a CVD-Al plug is proved to be one of the best via plug structures because of its low via resistance and high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4-μm, equal pitch and four-level interconnection View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Assessing the reliability of silicon nitride capacitors in a GaAs IC process

    Publication Year: 1998 , Page(s): 939 - 946
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    A method is presented for predicting the lifetime of silicon nitride (SiN) capacitors for different voltages and temperatures. The method builds on techniques used for analyzing Si MOS capacitors. Measuring breakdown voltages at different ramp rates and temperatures allows fast on-wafer determination of the field (γ) and temperature (Ea) acceleration parameters. Three different types of SiN were studied and were found to have similar values of γ and Ea, however intrinsic lifetimes varied by orders of magnitude View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A MOS-controlled high-voltage thyristor with low switching losses

    Publication Year: 1998 , Page(s): 957 - 965
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (636 KB)  

    A high-voltage phase-controlled symmetrical thyristor with MOS control was developed called the QCT. The QCT consists of two thyristor parts integrated on the same wafer; one MOS-controlled thyristor (MCT) with low conducting losses and a parallel conventional phase-controlled thyristor (PCT) with low switching losses. During the on-state both thyristor parts conduct the current. At commutation, the MCT-part is turned off, forcing the current over to the PCT. Thereby the QCT, even with high-voltage blocking capability, can have both low on-state losses and low switching losses, An experimental QCT for 5-10 kV has been designed and processed, having a diameter of 45 mm with a segmented MCT-part of 9-cm2 area with high carrier lifetime to achieve low conduction losses and a 1.5-cm2 PCT with low carrier lifetime to achieve low switching losses. The QCT has a conventional amplifying thyristor gate for turn-on and separate MOS-gates for turning off the MCT-part. The QCT was designed for a current handling capability of 400 A. It was shown that the reverse recovery charge could be reduced three to five times as compared to a device without this MOS-control View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Trapped charge distributions in thin (10 nm) SiO2 films subjected to static and dynamic stresses

    Publication Year: 1998 , Page(s): 881 - 888
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    Thin (10 nm) gate oxide MOS capacitors have been subjected to static and dynamic stress conditions. The evolution of the trapped charge distributions (characterized by average density and centroid) has been measured as a function of the stress time. The evolution of the average charge density for DC stresses shows that both polarities have identical trap generation rates and a constant average density of traps at breakdown. However, the final density of traps is much smaller for injection from the gate, so that the time-to-breakdown is also much shorter for this stress polarity. The evolution of the centroid shows that traps are always mainly generated near the cathodic interface. Unipolar dynamic stresses give results which are qualitatively very similar to those obtained under DC conditions and without a relevant frequency dependence. In contrast, bipolar stress experiments show significant qualitative differences, the frequency dependence being very important. In general, the trap generation and trapping rates are reduced in comparison to the DC and unipolar cases, this reduction being more important at high frequencies. In addition, the average density of trapped electrons at the breakdown is larger than that obtained in DC experiments. Both observations explain the tremendous increase in the mean-time-to-breakdown obtained under high-frequency stress conditions. The presented results are qualitatively explained in terms of microscopic degradation models View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Technology and characterization of diamond field emitter structures

    Publication Year: 1998 , Page(s): 977 - 985
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB)  

    In an effort to develop diamond field emitters with high current densities, diamond film technology compatible with Si integrated circuits is used to design new experiments for a systematic study of field emission as a function of sp3/sp2 ratio, grain size, doping level, patterning, field enhancement at the grain tips, and anode to emitter separation. Boron-doped polycrystalline diamond films with low sp3/sp2 ratios, high density of small grains and grain boundaries, and patterned structures result in high current densities and low emission fields. Electric fields to initiate emission, measured at J=0.01 mAcm-2, are in the range of 0.1-0.4 MV/cm depending upon diamond growth conditions. The results of this study have important consequences for diamond triode field emitter displays View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

Full Aims & Scope

Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego