IEEE Transactions on Computers

Issue 3 • March 1998

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Displaying Results 1 - 12 of 12
  • Optimal diagnosis of heterogeneous systems with random faults

    Publication Year: 1998, Page(s):298 - 304
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (226 KB)

    We consider the problem of fault diagnosis in multiprocessor systems. Processors perform tests on one another; fault-free testers correctly identify the fault status of tested processors, while faulty testers can give arbitrary test results. Processors fail with arbitrary probabilities and all failures are independent. The goal is to identify correctly the status of all processors, based on the se... View full abstract»

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  • Load balancing problems for multiclass jobs in distributed/parallel computer systems

    Publication Year: 1998, Page(s):322 - 332
    Cited by:  Papers (36)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    Load balancing problems for multiclass jobs in distributed/parallel computer systems with general network configurations are considered. We construct a general model of such a distributed/parallel computer system. The system consists of heterogeneous host computers/processors (nodes) which are interconnected by a generally configured communication/interconnection network wherein there are several ... View full abstract»

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  • Optimal circuits for parallel multipliers

    Publication Year: 1998, Page(s):273 - 285
    Cited by:  Papers (76)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (568 KB)

    We present new design and analysis techniques for the synthesis of parallel multiplier circuits that have smaller predicted delay than the best current multipliers. V.G. Oklobdzija et al. (1996) suggested a new approach, the Three-Dimensional Method (TDM), for Partial Product Reduction Tree (PPRT) design that produces multipliers that outperform the current best designs. The goal of TDM is to prod... View full abstract»

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  • Low-complexity bit-parallel canonical and normal basis multipliers for a class of finite fields

    Publication Year: 1998, Page(s):353 - 356
    Cited by:  Papers (122)  |  Patents (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    We present a new low-complexity bit-parallel canonical basis multiplier for the field GF(2m) generated by an all-one-polynomial. The proposed canonical basis multiplier requires m2-1 XOR gates and m2 AND gates. We also extend this canonical basis multiplier to obtain a new bit-parallel normal basis multiplier View full abstract»

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  • Optimal self-testing embedded parity checkers

    Publication Year: 1998, Page(s):313 - 321
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations wit... View full abstract»

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  • A simplified architecture for module (2n+1) multiplication

    Publication Year: 1998, Page(s):333 - 337
    Cited by:  Papers (52)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (136 KB)

    The module (2n+1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a module (2n+1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the module (2n+1) multiplication scheme i... View full abstract»

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  • Optimal elections in faulty loop networks and applications

    Publication Year: 1998, Page(s):286 - 297
    Cited by:  Papers (8)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (364 KB)

    Loop networks (or Hamiltonian circulant graphs) are a popular class of fault-tolerant network topologies which include rings and complete graphs. For this class, the fundamental problem of leader election has been extensively studied, assuming either a fault-free system or an upper-bound on the number of link failures. We consider loop networks where an arbitrary number of links have failed and a ... View full abstract»

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  • High performance fault-tolerant digital neural networks

    Publication Year: 1998, Page(s):357 - 363
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    Efficient implementation of neural networks requires high-performance architectures, while VLSI realization for mission-critical applications must include fault tolerance. Contemporaneous solution of such problems has not yet been completely afforded in the literature. This paper focuses both on data representation to support high-performance neural computation and on error detection to provide th... View full abstract»

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  • Logic testing of bridging faults in CMOS integrated circuits

    Publication Year: 1998, Page(s):338 - 345
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-influenced region of the fault... View full abstract»

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  • Regular sparse crossbar concentrators

    Publication Year: 1998, Page(s):363 - 368
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (208 KB)

    A bipartite concentrator is a single stage sparse crossbar switching device that can connect any m of its n⩾m inputs to its m outputs, possibly without the ability to distinguish their order. Fat-and-slim crossbars were introduced recently to show that bipartite concentrators can be constructed with a minimum number of crosspoints for any number of inputs and outputs. We generalize these graph... View full abstract»

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  • A VLSI architecture for approximate tree matching

    Publication Year: 1998, Page(s):346 - 352
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (180 KB)

    The distance between two labeled ordered trees, α and β, is the minimum cost sequence of editing operations (insertions, deletions, and substitutions) needed to transform a into β such that the predecessor-descendant relation between nodes and the ordering of nodes is not changed. Approximate tree matching has applications in genetic sequence comparison, scene analysis, error recov... View full abstract»

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  • Random pattern testability of memory control logic

    Publication Year: 1998, Page(s):305 - 312
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB)

    This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org