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Electron Devices, IEEE Transactions on

Issue 3 • Date Mar 1998

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Displaying Results 1 - 20 of 20
  • Role of rapid photothermal processing in process integration

    Page(s): 643 - 654
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    The smaller dimension devices and larger scales of integration are demanding constant reduction of the macroscopic and microscopic defects in the manufacturing of silicon integrated circuits. Increasing capital investment in manufacturing is forcing us toward processes and equipment that are effective not only in reduction of the cost of ownership but can also increase the effectiveness of equipment of current as well as future applications. Rapid thermal processing (RTP) based on incoherent light as the source of energy is playing an important role in the manufacturing of 300 nm and larger diameter wafers. The dominance of ultraviolet and vacuum ultraviolet photons in RTP results in rapid photothermal processing (RPP). The results presented in this paper show that the materials and devices processed by RPP are better than those processed by other thermal processes. This paper discusses the manufacturing science, operating principles of RPP and experimental results supporting its role in future process integration View full abstract»

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  • Process integration of an interlevel dielectric (ILDO) module using a building-in reliability approach

    Page(s): 655 - 664
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    Process integration is approached from a built-in reliability perspective in order to develop a pre-metal inter-level dielectric (ILDO) module which may be integrated into a submicron CMOS process with embedded nonvolatile memory. The approach involves developing a fundamental understanding of the process parameters that modulate parasitics and impact reliability. The benefit of such an approach is a relatively simple process integration while achieving a highly manufacturable and reliable process. Several ILDO films have been characterized to understand the physical and chemical composition, process parameter dependencies, and gettering properties in order to define a process window from which to integrate the most manufacturable process View full abstract»

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  • Making silicon nitride film a viable gate dielectric

    Page(s): 680 - 690
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    To extend the scaling limit of thermal SiO2 in the ultrathin regime when the direct tunneling current becomes significant, members of this author's research team at Yale University, in collaboration with the Jet Process Corporation, embarked on a program to explore the potential of silicon nitride as an alternative gate dielectric. In this paper, high-quality silicon nitride (or oxynitride) films made by a novel jet vapor deposition (JVD) technique are described. The JVD process utilizes a high-speed jet of light carrier gas to transport the depositing species onto the substrate to form the desired films. The film composition has been determined to consist primarily of Si and N, with some amounts of O and H. Metal-nitride-Si (MNS) capacitors based on the JVD nitride films deposited directly on Si exhibit relatively low densities of interface traps, fixed charge, and bulk traps. The interface traps at the nitride/Si interface exhibit different properties from those at the SiO2/Si interface in several aspects. In contrast to the conventional CVD silicon nitride, the high-field I-V characteristics of the JVD silicon nitride fit the Fowler-Nordheim (F-N) tunneling theory over four to five orders of magnitude in current, but do not fit at all the Frenkel-Poole (F-P) transport theory. This is consistent with the much lower concentration of electronic traps in the JVD silicon nitride. Results from the carrier separation experiment indicate that electron current dominates the gate current with very little hole contribution. Both theoretical calculation and experimental data indicate that the gate leakage current in JVD silicon nitride is significantly lower than that in silicon dioxide of the same equivalent oxide thickness. The breakdown characteristics of the JVD nitride are also respectable. Compared to their MOSFET counterparts, MNS transistors exhibit reduced low-field transconductance but enhanced high-field transconductance, perhaps due to the presence of border traps. As expected, the JVD silicon nitride films exhibit very strong resistance to boron penetration and oxidation at high temperatures. These properties, coupled with its room-temperature deposition process, make JVD silicon nitride an attractive candidate to succeed thermal SiO2 as an advanced gate dielectric in future generations of ULSI devices View full abstract»

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  • The physical and electrical effects of metal-fill patterning practices for oxide chemical-mechanical polishing processes

    Page(s): 665 - 679
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    In oxide chemical-mechanical polishing (CMP) processes, layout pattern dependent variation in the interlevel dielectric (ILD) thickness can reduce yield and impact circuit performance. Metal-fill patterning practices have emerged as a technique for substantially reducing layout pattern dependent ILD thickness variation. We present a generalizable methodology for selecting an optimal metal-fill patterning practice with the goal of satisfying a given dielectric thickness variation specification while minimizing the added interconnect capacitance associated with metal-fill patterning. Data from two industrial-based experiments demonstrate the beneficial impact of metal-fill on dielectric thickness variation, a 20% improvement in uniformity in one case and a 60% improvement in the other case, and illustrate that pattern density is the key mechanism involved. The pros and cons of two different metal-fill patterning practices-grounded versus floating metal-are explored. Criteria for minimizing the effect of floating or grounded metal-fill patterns on delay or crosstalk parameters are also developed based on canonical metal-fill structures. Finally, this methodology is illustrated using a case study which demonstrates an 82% reduction in ILD thickness variation View full abstract»

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  • DRAM technology perspective for gigabit era

    Page(s): 598 - 608
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    Many challenges emerge as the DRAM enters into a generation of the gigabit density era. Most of the challenges come from the shrink technology which scales down minimum feature size by a factor of 0.84 per year. The need for higher performance to narrow the bandwidth mismatch between fast processors and slower memories and lower power consumption drives the DRAM technology toward smaller cell size, faster memory cell operation, less power consumption, and longer data retention times. In addition, increasingly complicated wafer processing requires simple process. In this paper, the challenges brought from the extremely small minimum feature, high performance, and simple wafer processing will be discussed. The solutions to overcome the challenges will be described focusing on the memory cell scheme, lithography, device, memory cell capacitor, and metallization View full abstract»

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  • A stochastic wire-length distribution for gigascale integration (GSI). II. Applications to clock frequency, power dissipation, and chip size estimation

    Page(s): 590 - 597
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    For pt.I see ibid., vol.45, no.3, pp.580-9 (Mar. 1998). Based on Rent's Rule, a well-established empirical relationship, a complete wire-length distribution for on-chip random logic networks is used to enhance a critical path model; to derive a preliminary dynamic power dissipation model; and to describe optimal architectures for multilevel wiring networks that provide maximum interconnect density and minimum chip size View full abstract»

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  • Characteristics of low-energy BF2- or As-implanted layers and their effect on the electrical performance of 0.15-μm MOSFET's

    Page(s): 701 - 709
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    Low-energy ion implantation is investigated in detail as a method of fabricating ultrashallow and low resistance source/drain (S/D) extensions for 0.15-μm MOSFETs. High-temperature rapid thermal annealing (RTA) is found to be essential for obtaining a shallow junction with low sheet resistance. Significant degradation of carrier activation efficiency and a serious increase in sheet resistance were observed when the acceleration energy was lowered to 10 keV. Only 10% of the implanted atoms were activated by either 1-keV BF2or As-implantation. Both p- and n-MOSFETs were fabricated using low-energy (10-20 keV) BF2- and As-implantation with RTA. The p- and n-MOSFETs with a 0.15-μm gate length showed adequate short-channel characteristics, but their drive current was too low. The analysis of the S/D parasitic resistance shows that the low current drivability is due to the increase in the S/D sheet resistance of extensions for a p-MOSFET and the S/D edge resistance under the gate electrode for an n-MOSFET View full abstract»

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  • Undoped epitaxial Si channel n-MOSFET grown by UHV-CVD with preheating

    Page(s): 710 - 716
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    Undoped epitaxial channel n-MOSFET with high transconductance was developed. In order to obtain a good crystal quality of the epitaxial layer and, thus, to achieve high performance, it is important to reduce the oxygen concentration at the epitaxial Si/Si substrate interface. In this paper, we describe the relationship between the electrical characteristics and the surface density of oxygen at the epitaxial Si/Si substrate. We also describe the dependence of the electrical characteristics on epitaxial Si thickness. The gm of n-MOSFET with 40-nm epitaxial Si for 0.10-μm gate length was 630 mS/mm at V d-1.5 V, and the drain current was 0.77 mA/μm. This gm value in the case of the epitaxial Si channel is about 20% larger than that of bulk the MOSFET. These results show that epitaxial Si channel MOSFET's are useful for future high-speed ULSI devices View full abstract»

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  • A new device design methodology for manufacturability

    Page(s): 634 - 642
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    As future technology generations for integrated circuits continue to “shrink”, TCAD tools must be made more central to manufacturing issues; thus, yield optimization and design for manufacturing (DFM) should be addressed integrally with performance and reliability when using TCAD during the initial product design. This paper defines the goals for DFM in TCAD simulations and outlines a formal procedure for achieving an optimized result (ODFM). New design of experiments (DOE), weighted least squares modeling and multiple-objective mean-variance optimization methods are developed as significant parts of the new ODFM procedure. Examples of designing a 0.18-μm MOSFET device are given to show the impact of device design procedures on device performance distributions and sensitivity variance profiles View full abstract»

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  • A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation

    Page(s): 580 - 589
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (388 KB)  

    Based on Rent's Rule, a well-established empirical relationship, a rigorous derivation of a complete wire-length distribution for on-chip random logic networks is performed. This distribution is compared to actual wire-length distributions for modern microprocessors, and a methodology to calculate the wire-length distribution for future gigascale integration (GSI) products is proposed View full abstract»

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  • Process simplification in DRAM manufacturing

    Page(s): 609 - 619
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    DRAM manufacturers are driving the quest for integration friendly, simplified, and statistically-controlled process development. In the DRAM field, strong emphasis must be placed on “process simplification” as a means of staying cost effective and competitive. In order to examine process architecture and process integration, both at the module and system levels, it is emphasized that using correct statistical methods in conjunction with advanced technology is important. For simplified process development and integration, many aspects of the new process assessment are data driven. Also, it is critical to understand the source of variation in the process, obtain process stability, and assess the process capability relative to specifications of manufacturability and functionality. Statistical process control techniques are a requirement for interpreting the results of process capability studies, as will be discussed in this paper. In this paper, we have emphasized that both statistical methods and technological innovation are required for process optimization. We have investigated several examples that illustrate the methodology followed for the development of statistically controlled, production-worthy processes. The process improvement strategy is described both for gate stack and the DRAM cell. The focus of the results described here is both in the context of enhancing process capability for existing processes and evaluating alternate process options that can be accomplished through the use of advanced process technology View full abstract»

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  • Plasma-induced charging evaluation using SCA and PDM tools

    Page(s): 753 - 755
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    Plasma-induced charging has been characterized using unpatterned oxide wafer charging technique. Charging distributions correlate to gate oxide charging damage with antennae structure. Modification of the process by lowering pressure and increasing gas flow led to a significant decrease of the plasma-induced charging and the gate oxide damage View full abstract»

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  • Analysis of thin gate oxide degradation during fabrication of advanced CMOS ULSI circuits

    Page(s): 731 - 736
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    The electrical characteristics uniquely associated with the thin gate oxide degradation of the advanced CMOS technology in manufacturing were determined for the first time. They were different from Fowler-Nordheim (F-N) stress, and therefore, cannot be simulated by the F-N stress. The p+ thin gate oxides were found to be inherently more susceptible to gate oxide degradation than the n+ gate oxides. The p+ oxide degradation is caused by a combination of the process-induced defect and plasma charging. The nature of the defect and its formation were identified by electrical and physical analysis. The defect formation was modeled. The p-channel gate oxide degradation will be worse with gate oxide scaling, and may limit the device scaling View full abstract»

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  • Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFETs: uniformity, reliability, and dopant penetration of the gate oxide

    Page(s): 691 - 700
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    Although direct tunneling gate oxide MOSFETs are expected to be useful in high-performance applications of future large-scale integrated circuits (LSIs), there are many concerns related to their manufacture. The uniformity, reliability, and dopant penetration of 1.5-nm direct-tunneling gate oxide MOSFETs were investigated for the first time. The variation of oxide thickness in an entire 150-mm wafer was evaluated by TEM and electrical measurements. Satisfactory values of standard deviations in the TEM measurements and threshold voltage measurements for MOSFETs with a gate area of 5 μm×0.75 μm, were obtained. These values improved significantly in the case of MOS capacitors with larger gate areas. The oxide breakdown field and the reliability with respect to charge injection were evaluated for the 1.5-nm gate oxides and found to be better than those of thicker gate oxides. Dopant penetration was not observed in n+ polysilicon gates subjected to RTA at 1050°C for 20 s and furnace annealing at 850°C for 30 min. Although much more data will be required to judge the manufacturing feasibility, these results suggest that 1.5-nm direct-tunneling oxide MOSFETs are likely to have many practical applications View full abstract»

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  • Recent advances in process synthesis for semiconductor devices

    Page(s): 626 - 633
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    Recently, work has been started on a new methodology, called process synthesis, that has the potential to revolutionize integrated circuit (IC) process design in the same way that ASIC and microelectronics manufacturing science and technology (MMST) revolutionized circuit design and factory operation. This paper provides an overview of process synthesis, discusses synthesis methodologies, potential roadblocks to execution of this strategy, and presents recent progress in developing this capability View full abstract»

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  • 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation

    Page(s): 737 - 742
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    Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications View full abstract»

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  • 0.15-μm buried-channel p-MOSFETs with ultrathin boron-doped epitaxial Si layer

    Page(s): 717 - 721
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    We demonstrated silicon MOSFETs with a counter-doped ultrathin epitaxial channel grown by low-temperature UHV-CVD; this allows the channel region to be doped with boron with high precision. The boron concentration and epitaxial layer thickness can be chosen independently, and so it is easy to adjust the threshold voltage of the buried-channel p-MOSFETs with n-type polysilicon gates. It was confirmed that choosing an ultrathin epitaxial layer at 10 nm leads to suppression of the short-channel effects in buried-channel p-MOSFETs with gate length down to 0.15 μm, while maintaining an appropriate value of threshold voltage View full abstract»

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  • Advanced IC packaging for the future applications

    Page(s): 743 - 752
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    The performance of electronic equipment is improving rapidly. Portable electronic equipment requires smaller and thinner packaging systems for saving space and miniaturization. In addition, highly integrated, high-speed applications demand improved electrical performance to minimize noise effects. As a result of these considerations, the role of IC packaging has expanded from its traditional role of protecting the integrity and performance of an IC, to being a central factor in the development of electronic system concepts. In developing the optimum system, packaging technology must be a prime design consideration to ensure optimum performance, reliability, and cost. Soldering technology and Printed Wiring Board (PWB) routing density are two of the major technological issues facing miniaturized packaging systems today. Chip Scale Package (CSP), which is a new concept in packaging technology has been introduced. This is an ideal technology to enable the design and manufacture of the next generation of electronic equipment, while overcoming many of the technological issues facing system development View full abstract»

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  • Technology for advanced high-performance microprocessors

    Page(s): 620 - 625
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    This paper describes the development of logic technologies that meet the density, performance, power, and manufacturing requirements for advanced high-performance microprocessors. Aggressive scaling of MOS transistor dimensions along with reduced power supply provide devices with high performance, low power, and good reliability. Multiple layers of planarized aluminum interconnect with high aspect ratios are used to address the increasing importance of interconnect density and performance. Static RAM test vehicles with small 6-transistor cell sizes are used to develop these logic technologies and to provide early demonstrations of yield and performance capabilities. The manufacturing strategy includes development group ownership of the technology from inception to early manufacturing ramp, extensive reuse of prior generation process equipment and modules, and a “copy exactly” methodology to ensure successful process startup and ramp in multiple facilities View full abstract»

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  • Controlling plasma charge damage in advanced semiconductor manufacturing. Challenge of small feature size device, large chip size, and large wafer size

    Page(s): 722 - 730
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    During the ion implantation and plasma processing steps in IC manufacturing, the magnitude of charge damage on IC devices is often not as severe as the conventional charge damage antenna test structure estimate. On the other hand, the magnitude of the charge damage on the particular IC devices are often much more severe than the prediction of conventional antenna theory. Based on the new CMOS transistor and capacitor test structures (Spider's SPIDER) which closely simulates actual IC circuit interconnections, it can be found that the conductor lines (antennas) connected to the source, drain, and substrate affect the damage magnitude of the MOS gate significantly. This suggests that to have effective control on the plasma charge damage in the advanced semiconductor manufacturing, the antenna must be connected to the MOS transistor gate, also the interactions of the antennas connected to the source, drain, and substrate to the gate antenna have to be considered. Depending on the relative direction, distance, and size of the antennas connected to the gate, source, drain, and substrate, the magnitude of the charge-damage effects can he enhanced or exacerbated. Furthermore, to predict and automatically warn the potential charge-damage during the phase of IC layout design, a new charge antenna Design Rule Check (DRC) software has been developed to perform systematic layout checking with the consideration of the interactions of the ULSI interconnection lines, which become antennas connected to all four terminals of MOS transistors View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Editor-in-Chief
John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology