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Solid-State Circuits, IEEE Journal of

Issue 3 • Date Mar 1998

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Displaying Results 1 - 22 of 22
  • A low-power 170-MHz discrete-time analog FIR filter

    Publication Year: 1998 , Page(s): 417 - 426
    Cited by:  Papers (16)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (284 KB)  

    A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-μm CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9-tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution View full abstract»

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  • High-speed CMOS continuous-time complex graphic equalizer for magnetic recording

    Publication Year: 1998 , Page(s): 427 - 438
    Cited by:  Papers (5)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (332 KB)  

    A high-speed continuous-time CMOS analog adaptive equalizer for use in magnetic recording read channels is presented. The equalizer is implemented as the summation of several bandpass filters covering different frequency bands as in a graphic equalizer. The outputs from each filter are weighted by a complex coefficient and summed, which results in a linear combiner structure guaranteed to converge under least mean square (LMS) adaptation. System-level simulations of our “complex graphic equalizer (CGE)” show that its performance is comparable to that of a ten-tap finite impulse response (FIR) equalizer following a fourth-order low-pass filter when tested with two different sequence detectors: EPR4-MLSD and fixed delay tree search with decision feedback (FDTS/DF). A five-band tunable CGE has been fabricated using a 0.8-μm CMOS technology. The highest band of the fabricated CGE was centered at 80 MHz (corresponding to channel data rate of about 200 Msymbols/s). Measured dynamic range was 68 dB, and measured total harmonic distortion was only -75 dB while consuming 97 mW at 3.3 V. The measured CGE performance agreed within 0.2 dB with the simulation results for an FDTS/DF system with an ideal CGE operating at 2.5 user bits/PW50 View full abstract»

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  • Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation

    Publication Year: 1998 , Page(s): 449 - 453
    Cited by:  Papers (34)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (116 KB)  

    This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure View full abstract»

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  • 2-μm, 1.6-mW gated-gm sampler with 72-dB SFDR for f s=160 Ms/s and fin=320.25 MHz

    Publication Year: 1998 , Page(s): 400 - 409
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB)  

    The sampler is often the limitation in determining how early in the signal chain the conversion to discrete time can be done. We have fabricated a novel high-speed, wideband sampler core based upon a charge-domain gated-gm cell that has a measured spurious free dynamic range (SFDR) of 72 db for a sample rate of 160 Ms/s and an input frequency of 320.25 MHz. The sampling bandwidth is ~880 MHz. This performance is achieved at ~1% of the power and ~1% of the core area of a state-of-the-art track-and-hold circuit implemented in a much more advanced IC technology. Simulations indicate that far higher performance is possible in a more advanced process and with minor circuit optimization View full abstract»

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  • Variable supply-voltage scheme for low-power high-speed CMOS digital design

    Publication Year: 1998 , Page(s): 454 - 462
    Cited by:  Papers (98)  |  Patents (31)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (336 KB)  

    This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supple voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design View full abstract»

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  • Cyclostationary noise analysis of large RF circuits with multitone excitations

    Publication Year: 1998 , Page(s): 324 - 336
    Cited by:  Papers (73)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (400 KB)  

    This paper introduces a new, efficient technique for analyzing noise in large RF circuits subjected to true multitone excitations. Noise statistics in such circuits are time-varying, hence cyclostationary stochastic processes, characterized by harmonic power spectral densities (HPSDs), are used to describe noise. HPSDs are used to devise a harmonic-balance-based noise algorithm with the property that required computational resources grow almost linearly with circuit size and nonlinearity. Device noises with arbitrary spectra (including thermal, shot, and flicker noises) are handled, and input and output correlations, as well as individual device contributions, can be calculated. HPSD-based analysis is also used to establish the nonintuitive result that bandpass filtering of cyclostationary noise can result in stationary noise. Results from the new method are validated against Monte Carlo simulations. A large RF integrated circuit (>300 nodes) driven by a local oscillator (LO) tone and a strong RF signal is analyzed in less than two hours. The analysis predicts correctly that the presence of the RF tone leads to noise folding, affecting the circuit's noise performance significantly View full abstract»

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  • Automated low-power technique exploiting multiple supply voltages applied to a media processor

    Publication Year: 1998 , Page(s): 463 - 472
    Cited by:  Papers (93)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance View full abstract»

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  • A 1.6-GHz CMOS PLL with on-chip loop filter

    Publication Year: 1998 , Page(s): 337 - 343
    Cited by:  Papers (24)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    A 1.6-GHz phase locked loop (PLL) has been fabricated in a 0.6-μm CMOS technology. The PLL consists of an LC-tank circuit, divider, phase detector with charge pump, and an on-chip passive loop filter. When the oscillator is open loop, it exhibits -115 dBc/Hz phase noise at a 600-kHz offset from the carrier. The PLL occupies an active area of 1.6 mm2 and dissipates 90 mW from a single 3-V supply View full abstract»

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  • A digital adaptive beamforming QAM demodulator IC for high bit-rate wireless communications

    Publication Year: 1998 , Page(s): 367 - 377
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    A very large scale integration (VLSI) implementation of an integrated adaptive beamforming processor and quadrature amplitude modulation (QAM) demodulator which will be incorporated into a frequency-hopped spread spectrum portable receiver for 2.4-GHz industrial, scientific, and medical (ISM) band applications is presented. The chip performs coherent QAM demodulation of variable constellation size and complete adaptive beamforming processing including four-channel adaptive beamforming combining, a fully programmable training processor, a readable/writable system control processor, an acquisition state machine, and a microcontroller interface. Interleaving area intensive blocks such as the 49-tap square-root Nyquist filters and 12×12 b multipliers is employed to reduce chip area. This chip can operate as a stand-alone adaptive beamforming QAM demodulator, or it can work together with an adaptive equalizer for high bit rate indoor wireless applications. The core area of the chip is 6.22 mm×4.58 mm in 0.8-μm CMOS technology, and the power dissipation is 610 mW at 5 V and a 5 MBaud symbol rate. In a 2.2-dB signal-to-interference-and-noise ratio environment, the receiver chip achieves a link quality of 32.6 dB SNR by performing digital adaptive beamforming to null out interferers View full abstract»

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  • A 1.9-GHz silicon receiver with monolithic image filtering

    Publication Year: 1998 , Page(s): 378 - 386
    Cited by:  Papers (33)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    A 1.9-GHz fully monolithic silicon superheterodyne receiver front-end is presented; it consists of a low noise amplifier (LNA), a tunable image reject filter, and a Gilbert cell mixer integrated in one die. The receiver was designed to operate with a 1.9-GHz RF and a 2.2-GHz local oscillator (LO) for a 300-MHz IF. Two chip versions were fabricated on two different fabrication runs using a 0.5-μm bipolar technology with 25 GHz transit frequency (fT). Measured performance for the receiver front-end version 1, packaged and without input matching, was: conversion gain 33.5 dB, noise figure 4.9 dB, input IP3 -28 dBm, image rejection 53 dB (tuned to reject a 2.5-GHz image frequency), and 15.9 mA current consumption at +3 V. The image rejection was tunable from 2.4-2.63 GHz by means of an on-chip varactor. Version 2 had increased mixer degeneration for improved linearity. Its measured performance for the packaged receiver with its input matched to 50 Ω was: conversion gain 24 dB, noise figure 4.8 dB, input IP3 -19 dBm, and 65 dB image rejection for a 2.5-GHz image with an image tuning range from 2.34-2.55 GHz View full abstract»

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  • Low-power Viterbi decoder for CDMA mobile terminals

    Publication Year: 1998 , Page(s): 473 - 482
    Cited by:  Papers (47)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB)  

    An efficient state-sequential very large scale integration (VLSI) architecture and low-power design methodologies ranging from the system-level to the layout-level are presented for a large-constraint-length Viterbi decoder for code division multiple access (CDMA) digital cellular/personal communication services (PCS) applications. The low-power design approaches are also applicable to many other systems and algorithms. VLSI implementation issues and prototype fabrication results for a state-sequential Viterbi decoder for convolutional codes of rate 1/2 and constraint-length 9 are also described. The chip's core, consisting of approximately 65 k transistors, occupies 1.9 mm by 3.4 mm in a 0.8-μm triple-layer-metal n-well CMOS technology. The chip's measured total power dissipation is 0.24 mW at a 14.4 kb/s data-rate with 0.9216 MHz clocking at a supply voltage of 1.65 V. The Viterbi decoder presented here is the lowest power and smallest area core in its class, to the best of our knowledge View full abstract»

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  • A high-efficiency CMOS voltage doubler

    Publication Year: 1998 , Page(s): 410 - 416
    Cited by:  Papers (166)  |  Patents (47)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75% View full abstract»

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  • A 25 Ms/s 8-b-10 Ms/s 10-b CMOS data acquisition IC for digital storage oscilloscopes

    Publication Year: 1998 , Page(s): 492 - 496
    Cited by:  Papers (1)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    A data acquisition IC has been developed for digital storage oscilloscopes (DSOs). The entire DSO front-end except an input attenuator was integrated using 1-μm double-poly, double-metal (DPDM) CMOS process technology. In the analog-to-digital conversion, a time-interleaved successive approximation architecture effectively enables both 25 Ms/s 8-b and 10 Ms/s 10-b operation. The input signal conditioner consists of a variable gain amplifier (VGA) and a second-order programmable low-pass filter (LPF) using folded-cascode structures with current feedback circuits. The overall gain is externally controllable from 12 dB to 38 dB, and the bandwidth is programmable at 500 kHz, 5 MHz, and 25 MHz. The chip consumes 340 mW at the 25 Ms/s operating condition and less than 8 mW in the power-down mode from a single 5 V supply View full abstract»

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  • On-chip measurement of the jitter transfer function of charge-pump phase-locked loops

    Publication Year: 1998 , Page(s): 483 - 491
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    An all-digital technique for the measurement of the jitter transfer function of charge-pump phase-locked loops (PLLs) is introduced. Input jitter may be generated using one of two methods. Both rely on delta-sigma modulation to shape the unavoidable quantization noise to high frequencies. This noise is filtered by the low-pass characteristic of the device and has little impact on the test results. For an input-output response measurement, the output jitter is compared against a threshold. As the stimulus generation and output analysis circuits are digital, do not require calibration, and demand a small area overhead, this jitter transfer function measurement scheme may be placed on the die to adaptively tune a PLL after fabrication. The technique can also implement built-in self-test (BIST) for the characterization or manufacture test of PLLs. The validity of the scheme was verified experimentally with off-the-shelf components View full abstract»

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  • A transversal equalizer with an increased adaptation speed and tracking capability

    Publication Year: 1998 , Page(s): 503 - 507
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    A modification to the well-known least-mean-square (LMS) algorithm for adaptive equalizers is presented. It allows a flexible tradeoff between throughput rate and adaptation speed by adjusting the arithmetic expense per output sample. If the arithmetic expense is increased to that of recursive least-squares (RLS)-based algorithms, a comparable adaptation speed is achieved. A full-custom implementation of a transversal equalizer using timesharing by a factor of two and Booth-coded coefficients proves the feasibility and efficiency of the modified LMS. It achieves data rates of up to 75 MBaud in a 0.8-μm CMOS technology under worst case conditions. The convergence rate of the gradient lattice algorithm can be achieved by reducing the symbol rate to 15 MBaud. The modification requires about 15% additional area in the basic cell of the filter, a few additional control signals, and a buffer to store 40 input symbols View full abstract»

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  • A 2-V, low distortion, 1-GHz CMOS up-conversion mixer

    Publication Year: 1998 , Page(s): 359 - 366
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    A 1 GHz, very linear, CMOS up-conversion mixer is presented. The circuit is able to operate at a 2-V power supply. The topology has a true single-ended output stage which avoids the use of any balun. The total power consumption in both the mixers and the output stage is only 22 mW at 2 V. A profound analysis of the origins of distortion in the mixer has been performed. This study has resulted in the optimization of the linearity of the realized up-conversion mixer. The low power consumption, the low supply voltage, the high frequency performance, and the relatively large amplitude and low distortion single-ended off-chip output signal make the presented topology very suitable for wireless applications View full abstract»

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  • Computer-aided design considerations for mixed-signal coupling in RF integrated circuits

    Publication Year: 1998 , Page(s): 314 - 323
    Cited by:  Papers (45)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods View full abstract»

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  • A mixed-signal array processor with early vision applications

    Publication Year: 1998 , Page(s): 497 - 502
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    Many early vision tasks require only 6 to 8 b of precision. For these applications, a special-purpose analog circuit is often a smaller, faster, and lower power solution than a general-purpose digital processor, but the analog chips lack the programmability of digital image processors. This paper presents a programmable mixed-signal array processor which combines the programmability of a digital processor with the small area and low power of an analog circuit. Each processor cell in the array utilizes a digitally programmable analog arithmetic unit with an accuracy of 1.3%. The analog arithmetic unit utilizes a unique circuit that combines a cyclic switched-capacitor analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to perform addition, subtraction, multiplication, and division, Each processor cell, fabricated in a 0.8-μm triple-metal CMOS process, operates at a speed of 0.8 MIPS, consumes 1.8 mW of power at 5 V, and uses 700 μm by 270 μm of silicon area. An array of these processor cells performed an edge detection algorithm and a subpixel resolution algorithm View full abstract»

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  • Backside optical emission diagnostics for excess IDDQ

    Publication Year: 1998 , Page(s): 508 - 511
    Cited by:  Papers (3)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    Backside optical emission was used to diagnose excess quiescent current in a multimillion gate microprocessor. Emission images showed the current was due to FETs improperly set in a conducting state. The utility of backside optical emission for IC diagnostics is discussed, and requirements for optical detectors and sample preparation are considered View full abstract»

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  • Practical modeling for circuit simulation

    Publication Year: 1998 , Page(s): 439 - 448
    Cited by:  Papers (15)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    There is much more to modeling for circuit simulation than deriving a set of I(V), and perhaps Q(V), equations and extracting a SPICE MODEL card. Unfortunately, some practical aspects of modeling are often overlooked. This paper details common-sense guidelines for modeling and highlights common modeling problems. Particular emphasis is given on understanding accuracy requirements and numerical requirements, on ensuring that compact models are asymptotically correct, and on highlighting the real goal of modeling for circuit simulation: getting complete models for allowable device layouts working in the CAD system on a designer's desk View full abstract»

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  • Integrated circuit technology options for RFICs-present status and future directions

    Publication Year: 1998 , Page(s): 387 - 399
    Cited by:  Papers (102)  |  Patents (67)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    This paper will summarize the technology tradeoffs that are involved in the implementation of radio frequency integrated circuits for wireless communications. Radio transceiver circuits have a very broad range of requirements-including noise figure, linearity, gain, phase noise, and power dissipation. The advantages and disadvantages of each of the competing technologies-Si CMOS and bipolar junction transistors (BJTs), Si/SiGe HBTs and GaAs MESFETs, PHEMTS and HBTs will be examined in light of these requirements View full abstract»

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  • A micropower CMOS, direct-conversion, VLF receiver chip for magnetic-field wireless applications

    Publication Year: 1998 , Page(s): 344 - 358
    Cited by:  Papers (10)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (364 KB)  

    A micropower CMOS, direct-conversion very low frequency (VLF) receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, phase locked loop (PLL)-synthesized receiver covers a frequency range of 10-82 kHz and provides both analog and 9-b digital baseband I and Q outputs. Digital I and Q outputs are accumulated in a companion digital chip which provides baseband signal processing. Emphasis is plated on the receiver micropower RF preamplifier which uses a lateral bipolar input device because of the significant increase in flicker noise illustrated for PMOS devices in weak inversion. Lateral bipolar transistors are also utilized in the mixer and IF stages for low flicker noise and low dc offsets. Special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 μV noise floor in 300 Hz BW), and local oscillator feedthrough is indiscernible in the RF preamplifier output noise spectrum. The 100% duty-cycle receiver, intended for miniature, battery-operated wireless applications, operates approximately four months at 80 μA from a 6-V, 220-mA-hr battery View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan