# IEE Proceedings - Computers and Digital Techniques

## Filter Results

Displaying Results 1 - 7 of 7
• ### Logic synthesis of a PLL phase frequency detector

Publication Year: 1997, Page(s):381 - 385
Cited by:  Papers (1)
| | PDF (428 KB)

The design of the phase frequency detector of the phase-locked loop (PLL) of the Strongarm microprocessor has been designed according to an asynchronous design methodology based on negative gates. This methodology is based on a CMOS gate delay model which takes into account the delays of input inverters. The resulting phase frequency detector presents a better performance than the conventional cir... View full abstract»

• ### Design and modelling of a high performance differential bipolar self-timed microprocessor

Publication Year: 1997, Page(s):371 - 380
Cited by:  Papers (2)
| | PDF (992 KB)

Current interest in self-timed systems is motivated by the area, power and design effort required for the global clock of VLSI synchronous designs. A self-timed data-path, based on the ARM (Advanced RISC Machine) processor, using micropipeline' control techniques has been developed for a newly updated high-performance differential bipolar technology. This paper describes the architectural model p... View full abstract»

• ### Security management architecture for access control to network resources

Publication Year: 1997, Page(s):362 - 370
Cited by:  Papers (2)  |  Patents (4)
| | PDF (884 KB)

Threats to network resources increase exponentially with the growth of the network/users and with technological developments. In this paper, the authors describe a security management framework for access control to network resources. They deal with this in three steps. In the first part, user access control to a given network is discussed. In the second part, access control to the network resourc... View full abstract»

• ### Bit-serial multiplication in GF(2m) using irreducible all-one polynomials

Publication Year: 1997, Page(s):391 - 393
Cited by:  Papers (7)
| | PDF (260 KB)

Two architectures for carrying out bit-serial multiplication in the GF(2m) finite field are presented where the defining irreducible polynomial for the field is an all-one polynomial. The multipliers presented have low hardware requirements, regular structures and are therefore suitable for VLSI implementation View full abstract»

• ### Logic models for continuous time

Publication Year: 1997, Page(s):353 - 361
| | PDF (892 KB)

Logic simulation has been used for decades and is now part of all CAD systems, and yet theoretical aspects of the analogue-to-digital abstraction still need to be studied and formalised. The paper discusses the preservation of analogue circuit properties (continuity, causality and time invariance), during the construction of logic models. Modelling the analogue circuit behaviour and constructing a... View full abstract»

• ### Digital signature with a subliminal channel

Publication Year: 1997, Page(s):387 - 389
Cited by:  Papers (12)
| | PDF (360 KB)

A subliminal channel is a covert communication channel to send a message to an authorised receiver; this message cannot be discovered by any unauthorised receiver. There are some applications that can take advantage of this by hiding secret messages in this subliminal channel. For example, a credit card provider can hide the card holder's credit history and credit limit in a digital signature for ... View full abstract»

• ### Critique of the paper Novel design of arithmetic coding for data compression'

Publication Year: 1997, Page(s):394 - 396
| | PDF (348 KB)

The author provides a critique of the paper `Novel design of arithmetic coding for data compression' by J. Jiang (ibid., vol. 142, no. 6, pp. 419-24, 1995). A number of problems in the proposed implementation are pointed out and the origins of some of the described mechanisms are discussed View full abstract»

## Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.

Full Aims & Scope