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IEEE Design & Test of Computers

Issue 3 • June 1989

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Displaying Results 1 - 4 of 4
  • Parallel simulated annealing: accuracy vs. speed in placement

    Publication Year: 1989, Page(s):8 - 34
    Cited by:  Papers (23)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2196 KB)

    The techniques that researchers have used to control error in VLSI placement are surveyed. The author discusses the application of parallelism, synchronization with serial subsets, combining algorithms, periodic synchronization, shared-memory implementation, local-memory implementation, and connection Machine implementation. The issues of temporary versus cumulative error, task allocation, and err... View full abstract»

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  • Engineering a device for electron-beam probing

    Publication Year: 1989, Page(s):36 - 42
    Cited by:  Papers (7)  |  Patents (35)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1125 KB)

    The principles of electron-beam probing for diagnostic work are described. Guidelines are presented to help users of electron-beam probe stations optimize their IC design and manufacturing procedures for electron-beam probing. The guidelines cover: observability, maintaining line of sight, direct versus indirect measuring, using test points, accuracy, improving signal-to-noise ratio, reducing cros... View full abstract»

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  • Scan design at NEC

    Publication Year: 1989, Page(s):50 - 51
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (574 KB)

    The authors describe scan path, NEC's implementation of the scan design approach to design for testability. Designers at NEC have found that scan path greatly contributes to the reduced testing and maintenance cost of their products. The authors discuss several implementations of scan design and compare four implementations, including two scan-path techniques.<> View full abstract»

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  • A built-in test module for fault isolation

    Publication Year: 1989, Page(s):58 - 65
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (625 KB)

    A broad-level implementation of signature analysis that uses a built-in test module called a testing switch is presented. It is shown how board designers can incorporate the testing-switch modules to reduce the time it takes to isolate faulty chips. Both the test time and the power overhead are better with the testing-switch implementation than with schemes using built-in logic block observer circ... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty