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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Issue 11 • Nov 1997

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Displaying Results 1 - 15 of 15
  • Improved model reduction procedure for 2-D separable denominator digital systems

    Publication Year: 1997, Page(s):979 - 982
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (156 KB)

    An improved procedure is presented for the model reduction of 2-D separable denominator digital systems H(z1,z2). The proposed procedure is based on modifying the factorization H(z1 ,z2)=H2(z2)H1(z1 ) and minimizing an existing frequency error bound developed by Zhou, Li, and Lee (1991). In terms of small actua... View full abstract»

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  • A scalable low voltage analog Gaussian radial basis circuit

    Publication Year: 1997, Page(s):977 - 979
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (84 KB)

    Gaussian basis function (GBF) networks are powerful systems for learning and approximating complex input-output mappings. Networks composed of these localized receptive field units trained with efficient learning algorithms have been simulated solving a variety of interesting problems. For real-time and portable applications however, direct hardware implementation is needed. We describe experiment... View full abstract»

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  • Optimized reduced sample rate sigma-delta modulation

    Publication Year: 1997, Page(s):896 - 906
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (392 KB)

    An optimized reduced sample rate sigma-delta modulation technique for application in digital to analog conversion is presented. A general framework of a sigma-delta modulating topology where the major arithmetic computation is done at a rate of an integer fraction of the bit-stream rate Is proposed and analyzed. The effectiveness of the technique is illustrated using simulations of second- and thi... View full abstract»

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  • Synthesis of high-speed pass-transistor logic

    Publication Year: 1997, Page(s):974 - 976
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (88 KB)

    The authors present new pass-transistor logic which contains fewer transistors and has better performance than Hitachi's double pass-transistor logic (DPL). The new CMOS logic, dual value logic (DVL), is characterized by excellent speed and low power View full abstract»

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  • Designing fuzzy logic systems

    Publication Year: 1997, Page(s):885 - 895
    Cited by:  Papers (47)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    We present a formulation of a fuzzy logic system (FLS) that can be used to construct nonparametric models of nonlinear processes, given only input-output data. In order to effectively construct such models, we discuss several design methods with different properties and features. We compare and illustrate systems designed with each one of the methods, using an example on the predictive modeling of... View full abstract»

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  • ECL storage elements: modeling of faulty behavior

    Publication Year: 1997, Page(s):970 - 974
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    Bipolar emitter coupled logic (ECL) devices can now be fabricated at very high densities and much lower power consumption. Behavior of two different ECL storage element implementations are examined in the presence of physical faults. While fault models for some implementations of CMOS storage elements have been examined, not much attention has been paid to ECL storage elements. The conventional st... View full abstract»

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  • A new fast DCT algorithm and its systolic VLSI implementation

    Publication Year: 1997, Page(s):959 - 962
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (152 KB)

    The authors present a new fast algorithm along with its systolic array implementation for computing the N-point discrete cosine transform (DCT), where N is a power of two. The architecture requires log2 N multipliers and can evaluate one complete N-point DCT (i.e., N transform samples) every N clock cycles. Due to the features of regularity and modularity, it is well suited to VLSI impl... View full abstract»

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  • Poly-phase sigma-delta modulation

    Publication Year: 1997, Page(s):915 - 923
    Cited by:  Papers (8)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (236 KB)

    A new circuit is described for the implementation of analog sigma-delta modulation. It is based upon the use of a poly-phase sampler with the aim of obtaining high over-sampling ratios at low clock frequencies. A detailed analysis of second-order systems is made to predict its performance. The basic modeling comprises the incorporation of sampling noise within limit cycle oscillations of the modul... View full abstract»

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  • Practical design rules for minimax linear phase diamond-shaped 2-D FIR low-pass filters

    Publication Year: 1997, Page(s):966 - 970
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    Diamond-shaped filters are used as antialiasing filters in the conversion between images sampled on the rectangular and quincunx sampling grids. Here we investigate some characteristics of the linear phase diamond-shaped low-pass filters and present a set of design rules applicable to the design of such filters optimal in the minimax error sense. The design rules provide good estimates for the min... View full abstract»

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  • Multifunction biquadratic filters using current conveyors

    Publication Year: 1997, Page(s):956 - 958
    Cited by:  Papers (67)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Some novel multifunction biquadratic filters with voltage gain, each of which employs four current conveyors, two grounded capacitors, and three-five resistors, are presented. Each proposed circuit offers the following advantageous features: realization of different biquadratic filter signals from the same configuration, no requirements for component matching conditions, employment of only two gro... View full abstract»

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  • Analog-to-digital conversion via duty-cycle modulation

    Publication Year: 1997, Page(s):907 - 914
    Cited by:  Papers (89)  |  Patents (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (244 KB)

    An exchange of the amplitude axis for the time axis offers a possibility of overcoming resolution problems in analog-to-digital conversion in low-voltage CMOS circuits and/or of circumventing special resistor options in silicided processes. This exchange can be effected via some form of duty-cycle modulation. For its implementation a circuit configuration is described, consisting of an asynchronou... View full abstract»

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  • An adaptive gain control with a variable step size for use in high-speed data communication systems

    Publication Year: 1997, Page(s):962 - 966
    Cited by:  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (160 KB)

    A high-precision adaptive gain control is an important function in high-speed data communication systems. The nonsymmetric statistics of the received signal results in a biased value of gain, particularly if 2B1Q line code is used, which contains a periodically repeated synchronization word, i.e., a Barker sequence. A bias-free gain is obtained using a step size that depends on the statistics of t... View full abstract»

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  • A new quasi-Newton adaptive filtering algorithm

    Publication Year: 1997, Page(s):924 - 934
    Cited by:  Papers (25)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    A new algorithm for FIR adaptive filters based on the quasi-Newton class of optimization algorithms is described. A series of theorems demonstrating the stability of the algorithm, boundedness and positive definiteness of the estimated autocorrelation matrix of the input signal are provided. The internal variables of the algorithm and their effect are also investigated in order to provide a better... View full abstract»

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  • A mathematical basis for power-reduction in digital VLSI systems

    Publication Year: 1997, Page(s):935 - 951
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (504 KB)

    Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to: (1) derive lower bounds on the power dissipation in digital systems; and (2) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process... View full abstract»

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  • Roundoff noise analysis of state-space digital filters implemented on floating-point digital signal processors

    Publication Year: 1997, Page(s):952 - 955
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (148 KB)

    An expression is obtained for the output floating-point roundoff noise variance of a general Nth-order state-space digital filter with zero-mean white noise input signal. This expression is then simplified for the case there the filter is implemented on a floating-point digital signal processor. Such processors carry extended precision bits in the accumulation register, so that the primary source ... View full abstract»

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Aims & Scope

This title ceased production in 2003. The current updated title is IEEE Transactions on Circuits and Systems II: Express Briefs.

Full Aims & Scope