Issue 7 • Date Jul 1997
Filter Results
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Symbolic two-level minimization
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PDF (624 KB)
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On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits
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PDF (172 KB)
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Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning
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PDF (200 KB)
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Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations
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PDF (372 KB)
Aims & Scope
Contains articles on methods, algorithms, and human-machine interfaces for physical and logical design, including: planning, synthesis, partitioning, modeling, simulation, layout, verification, testing, and documentation of integrated-circuit and systems designs of all complexities.
Meet Our Editors
Editor-in-Chief
Sachin Sapatnekar
University of Minnesota
Dept. of Electrical and Computer Engineering
4-174 Keller Hall, 200 Union Street SE
Minneapolis, MN 55455 55455 USA
sachin@umn.edu


