By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 7 • Date Jul 1997

Filter Results

Displaying Results 1 - 13 of 13
  • Logic synthesis of multilevel circuits with concurrent error detection

    Publication Year: 1997 , Page(s): 783 - 789
    Cited by:  Papers (53)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB)  

    This paper presents a procedure for synthesizing multilevel circuits with concurrent error detection. All errors caused by single stuck-at faults are detected using a parity-check code. The synthesis procedure (implemented in Stanford CRCs TOPS synthesis system) fully automates the design process, and reduces the cost of concurrent error detection compared with previous methods. An algorithm for selecting a good parity-check code for encoding the circuit outputs is described. Once the code has been selected, a new procedure called structure-constrained logic optimization is used to minimize the area of the circuit as much as possible while still using a circuit structure that ensures that single stuck-at faults cannot produce undetected errors. It is proven that the resulting implementation is path fault secure, and when augmented by a checker, forms a self-checking circuit. The actual layout areas required for self-checking implementations of benchmark circuits generated with the techniques described in this paper are compared with implementations using Berger codes, single-bit parity, and duplicate-and-compare. Results indicate that the self-checking multilevel circuits generated with the procedure described here are significantly more economical View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The inversion algorithm for digital simulation

    Publication Year: 1997 , Page(s): 762 - 769
    Cited by:  Papers (8)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB)  

    The inversion algorithm is an event-driven algorithm, whose performance rivals or exceeds that of levelized compiled code simulation, even at activity rates of 50% or more. The inversion algorithm has several unique features, the most remarkable of which is the size of the run-time code. The basic algorithm can be implemented using no more than a page of run-time code, although in practice, it is more efficient to provide several different variations of the basic algorithm. The run-time code is independent of the circuit under test, so the algorithm can be implemented either as a compiled code or an interpreted simulator with little variation in performance. Because of the small size of the run-time code, the run-time portions of the inversion algorithm can be implemented in assembly language for peak efficiency, and still can be retargeted for new platforms with little effort View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations

    Publication Year: 1997 , Page(s): 734 - 744
    Cited by:  Papers (56)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (372 KB)  

    A novel technique is presented which employs pole analysis via congruence transformations (PACT) to reduce RC networks in a well-conditioned manner. Pole analysis is shown to be more efficient than Pade approximations when the number of network ports is large, and congruence transformations preserve the passivity (and thus absolute stability) of the networks. The error incurred by reducing the networks is shown to be bounded by values which are fully selectable by the user. Networks are represented by admittance matrices throughout the analysis, and this representation both simplifies interfacing the reduced networks with circuit simulators and facilitates realization of the reduced networks using RC elements. A prototype SPICE-in, SPICE-out, network reduction CAD tool called RCFIT is detailed, and examples are presented which demonstrate the accuracy and efficiency of the PACT algorithm View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Symbolic two-level minimization

    Publication Year: 1997 , Page(s): 692 - 708
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    In this paper, we present a symbolic minimization procedure to obtain optimal two-level implementations of finite-state machines. Encoding based on symbolic minimization consists of optimizing the symbolic representation, and then transforming the optimized symbolic description into a compatible two-valued representation by satisfying encoding constraints (bitwise logic relations) imposed on the binary codes that replace the symbols. Our symbolic minimization procedure captures the sharing of product terms due to ORing effects in the output part of a two-level implementation of the symbolic cover. Face, dominance, and disjunctive constraints are generated. Product terms are accepted in a symbolic minimized cover only when they induce compatible encoding constraints. At the end, a set of codes that satisfy all constraints is computed. The quality of this synthesis procedure is shown by the fact that the cardinality of the cover obtained by symbolic minimization and of the cover obtained by replacing the codes in the initial cover and then minimizing it with ESPRESSO are very close. Experiments show that in some cases, our procedure improves on the best results of state-of-art tools View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Testing analog and mixed-signal integrated circuits using oscillation-test method

    Publication Year: 1997 , Page(s): 745 - 753
    Cited by:  Papers (51)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    A new low-cost test method for analog integrated circuits, called the oscillation test, is presented. During the test mode, the circuit under test (CUT) is converted to a circuit that oscillates. Faults in the CUT which deviate the oscillation frequency from its tolerance band can be detected. Using this test method, no test vector is required to be applied. Therefore, the test vector generation problem is eliminated, and the test time is very small because only a single output frequency is evaluated for each CUT. The oscillation frequency may be considered as a digital signal and therefore can be evaluated using pure digital circuitry. These characteristics imply that the oscillation-test strategy is very attractive for wafer-probe testing as well as final production testing. In this note, the validity of the proposed test method has been verified throughout various examples such as operational amplifiers, amplifiers, filters, and analog-to-digital converters (ADCs). The simulations and practical implementation results affirm that the presented method assures a high fault coverage View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Combining problem reduction and adaptive multistart: a new technique for superior iterative partitioning

    Publication Year: 1997 , Page(s): 709 - 717
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (200 KB)  

    VLSI netlist partitioning has been addressed chiefly by iterative methods (e.g. Kernighan-Lin and Fiduccia-Mattheyses) and spectral methods (e.g. Hagen-Kahng). Iterative methods are the de facto industry standard, but suffer diminished stability and solution quality when instances grow large. Spectral methods have achieved high-quality solutions, particularly for the ratio cut objective, but suffer excessive memory requirements and the inability to capture practical constraints (preplacements, variable module areas, etc.). This work develops a new approach to Fiduccia-Mattheyses (FM)-based iterative partitioning. We combine two concepts: (1) problem reduction using clustering and the two-phase FM methodology and (2) adaptive multistart, i.e. the intelligent selection of starting points for the iterative optimization, based on the results of previous optimizations. The resulting clustered adaptive multistart (CAMS) methodology substantially improves upon previous partitioning results in the literature, for both unit module areas and actual module areas, and for both the min-cut bisection and minimum ratio cut objectives. The CAMS method is surprisingly fast and has very stable solution quality, even for large benchmark instances. It has been applied as the basis of a clustering methodology within an industry placement tool View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Explicit and implicit algorithms for binate covering problems

    Publication Year: 1997 , Page(s): 677 - 691
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (424 KB)  

    We survey techniques for solving binate covering problems, an optimization step often occurring in logic synthesis applications. Standard exact solutions are found with a branch-and-bound exhaustive search, made more efficient by bounding away regions of the search space. Standard approaches are said to be explicit because they work on a direct representation of the binate table, usually as a matrix. Recently, covering problems involving large tables have been attacked with implicit techniques. They are based on the representation by reduced-ordered binary decision diagrams of an encoding of the binate table. We show how table reductions, computation of a lower bound, and of a branching column can be performed on the table so represented. We report experiments for two different applications that demonstrate that implicit techniques handle instances beyond the reach of explicit techniques. Various aspects of our original research are presented for the first time, together with a selection of the most important old and new results scattered in many sources View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On-line detection of bridging and delay faults in functional blocks of CMOS self-checking circuits

    Publication Year: 1997 , Page(s): 770 - 776
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    This paper investigates the detection of parametric bridging and delay faults affecting the functional block of CMOS self-checking circuits (SCCs). As far as these faults are concerned, classical definitions are shown to become ambiguous because they are entirely based on logic considerations. Thus, new definitions are proposed here to consider the analog and dynamic effects of such faults, and to ensure that they do not produce any problem at the system level. Moreover, electrical level design rules aimed at satisfying these conditions are proposed for self-checking circuits with combinational functional blocks. The problem of their practicability and effectiveness is analyzed in detail, and is shown by means of significant examples View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A phase assignment method for virtual-wire-based hardware emulation

    Publication Year: 1997 , Page(s): 776 - 783
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    In a hardware emulator consisting of multiple field-programmable gate arrays (FPGAs), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins. Virtual wire technology not only increases the inter-FPGA communication capability, but it also increases the logic resource utilization by means of time division multiplexing (TDM). TDM allows one physical wire to be shared by multiple logical wires. For TDM to be effective, each transportation of an inter-FPGA signal must be carefully assigned to a slot of the time division. In this note, we show that the phase assignment problem is exactly same as the resource-constrained operation scheduling problem. We adopt the static-list scheduling heuristic for the task, and present some experimental results on a set of benchmark circuits from the MCNC. The experiments show that the proposed method can increase the number of effective I/O pins as many as ten times View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Improving a nonenumerative method to estimate path delay fault coverage

    Publication Year: 1997 , Page(s): 759 - 762
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (84 KB)  

    A recently proposed method obtains path delay fault coverages by estimating the count of the number of tested faults instead of actually enumerating them. The estimate becomes pessimistic when several paths share a set of lines. In this communication, we present a continuum of improved approximations for the counting method, approaching exact fault simulation, to allow tradeoffs between accuracy and complexity. Higher accuracy is obtained at the expense of CPU time. We propose the use of flags corresponding to fixed-length path segments. A flag indicates whether or not the segment has been included in a previously detected path fault. A path fault, detected by a pair of vectors, is counted as a new detection only if it includes at least one segment not included in any previously tested path fault. The results show that as the length of segments is increased, the accuracy becomes close to that of the exact fault simulation, even with small segment lengths View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical estimation of signal transition activity from word-level statistics

    Publication Year: 1997 , Page(s): 718 - 733
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (584 KB)  

    Presented in this paper is a novel methodology to determine the average number of transitions in a signal from its word-level statistical description. The proposed methodology employs: (1) high-level signal statistics, (2) a statistical signal generation model, and (3) the signal encoding (or number representation) to estimate the transition activity for that signal. In particular, the signal statistics employed are mean (μ), variance (σ2), and autocorrelation (ρ). The signal generation models considered are autoregressive moving-average (ARMA) models. The signal encoding includes unsigned, one's complement, two's complement, and sign-magnitude representations. First, the foilowing exact relation between the transition activity (ti), bit-level probability (pi), and the bit-level autocorrelation (ρi) for a single bit signal bi is derived: ti=2pi (1-pi)(1-ρi) (1). Next, two techniques are presented which employ the word-level signal statistics, the signal generation model, and the signal encoding to determine ρi (i=0, ···, B-1) in (1) for a B-bit signal. The word-level transition activity T is obtained as a summation over ti (i=0,···, B-1); where ti is obtained from (1). Simulation results for 16-bit signals generated via ARMA models indicate that an error in T of less than 2% can be achieved. Employing AR(1) and MA(10) models for audio and video signals, the proposed method results in errors of less than 10%. Both analysis and simulations indicate the sign-magnitude representation to have lower transition activity than unsigned, ones' complement, or two's complement. Finally, the proposed method is employed in estimation of transition activity in digital signal processing (DSP) hardware. Signal statistics are propagated through various DSP operators such as adders, multipliers, multiplexers, and delays, and then the transition activity T is calculated. Simulation results with ARMA inputs show that errors less than 4% are achievable in the estimation of the total transition activity in the filters. Furthermore, the transpose form structure is shown to have fewer signal transitions as compared to the direct form structure for the same input View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Implicit computation of compatible sets for state minimization of ISFSMs

    Publication Year: 1997 , Page(s): 657 - 676
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    The computation of sets of compatibles of incompletely specified finite-state machines (ISFSMs) is a key step in sequential synthesis. This paper presents implicit computations to obtain sets of maximal compatibles, compatibles, prime compatibles, implied sets, and class sets. The computations are implemented by means of BDDs that realize the characteristic functions of these sets. We have demonstrated with experiments from a variety of benchmarks that implicit techniques allow us to handle examples exhibiting a number of compatibles up to 21500, an achievement outside the scope of programs based on explicit enumeration. We have shown, in practice, that ISFMSs with a very large number of compatibles may be produced as intermediate steps of logic synthesis algorithms, for instance, in the case of asynchronous synthesis. This shows that the proposed approach not only has a theoretical interest, but also practical relevance for current logic synthesis applications, as shown by its application to ISFSM state minimization View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A fast algorithm for minimizing the Elmore delay to identified critical sinks

    Publication Year: 1997 , Page(s): 753 - 759
    Cited by:  Papers (4)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (164 KB)  

    A routing algorithm that generates a Steiner route for a set of sinks with near optimal Elmore delay to the critical sink is presented. The algorithm outperforms the best existing alternative for Elmore-delay-based critical sink routing. With no critical sinks present, the algorithm produces routes comparable to the best previously existing Steiner router. Since performance-oriented layout generators employ iterative techniques that require a large number of calls to the routing algorithm for layout evaluation, a fast algorithm for routing is desirable. The algorithm presented here has a fast (O(n2), where n is the number of points) and practical implementation using simple data structures and techniques View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu