IEEE Transactions on Computers

Issue 12 • Dec. 1997

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Displaying Results 1 - 13 of 13
  • 1997 Index

    Publication Year: 1997, Page(s):1396 - 1408
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    Freely Available from IEEE
  • Evaluating dynamic failure probability for streams with (m, k)-firm deadlines

    Publication Year: 1997, Page(s):1325 - 1337
    Cited by:  Papers (19)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (332 KB)

    A real-time stream is said to have (m, k)-firm deadlines if at least m out of any k-consecutive customers from the stream must meet their respective deadlines. Such a stream is said to have encountered a dynamic failure if fewer than m out of any k consecutive customers meet their deadlines. Hamdaoui and Ramanathan recently proposed a scheduling policy called Distance Based Priority (DBP) in which... View full abstract»

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  • A new parallel algorithm for time-slot assignment in hierarchical switching systems

    Publication Year: 1997, Page(s):1387 - 1395
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    The time-slot assignment (TSA) problem in a TDM switching system is to find a conflict-free assignment of traffic-units to slots such that the frame-length is minimized. In this paper, we develop a new parallel algorithm for the TSA problem in hierarchical switching systems (HSS). To design the parallel algorithm, we first reduce the TSA problem to the problem of routing permutations in three-stag... View full abstract»

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  • Optimal parallel routing in star networks

    Publication Year: 1997, Page(s):1293 - 1303
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    Star networks have recently been proposed as attractive alternatives to the popular hypercube for interconnecting processors on a parallel computer. In this paper, we present an efficient algorithm that constructs an optimal parallel routing in star networks. Our result improves previous results for the problem View full abstract»

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  • Incremental reconfiguration and load adjustment in adaptive real time systems

    Publication Year: 1997, Page(s):1313 - 1324
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (232 KB)

    We provide a framework for discussing how to adjust load in order to handle periodic processes whose timing parameters vary with time. The schedulability of adjustable periodic processes by a preemptive fixed priority scheduler is formulated in terms of a configuration selection problem for which a PTIME solution is shown. When the list of allowable configurations is implicitly given by a set of s... View full abstract»

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  • Performance optimization of checkpointing schemes with task duplication

    Publication Year: 1997, Page(s):1381 - 1386
    Cited by:  Papers (30)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB)

    In checkpointing schemes with task duplication, checkpointing serves two purposes: detecting faults by comparing the processors' states at checkpoints, and reducing fault recovery time by supplying a safe point to rollback to. In this paper, we show that, by tuning the checkpointing schemes to a given architecture, a significant reduction in the execution time can be achieved. The main idea is to ... View full abstract»

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  • The case for chaotic adaptive routing

    Publication Year: 1997, Page(s):1281 - 1292
    Cited by:  Papers (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (416 KB)

    Chaotic routers are randomizing, nonminimal adaptive packet routers designed for use in the communication networks of parallel computers. Chaotic routers combine the flexibility found in adaptive routing with a design simple enough to be competitive with the most streamlined oblivious routers. We review chaotic routing and compare it with other contemporary network routing approaches, including st... View full abstract»

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  • Processor assignment and execution sequence for multiversion software

    Publication Year: 1997, Page(s):1371 - 1377
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    Consider the problem of assigning N software versions of a multiversion software to M processors for execution. When a processor completes executing a software version, it sends the output to a voter immediately. The voter executes a voting strategy to estimate the correct output. When it has made a sufficiently reliable estimation (e.g., it has received [(N/2)] identical outputs under majority vo... View full abstract»

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  • Allocation of periodic task modules with precedence and deadline constraints in distributed real-time systems

    Publication Year: 1997, Page(s):1338 - 1356
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    This paper addresses the problem of allocating (assigning and scheduling) periodic task modules to processing nodes in distributed real-time systems subject to task precedence and timing constraints. Using the branch-and-bound technique, a module allocation scheme is proposed to find an “optimal” allocation that maximizes the probability of meeting task deadlines. The task system withi... View full abstract»

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  • A formally verified sorting certifier

    Publication Year: 1997, Page(s):1304 - 1312
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (288 KB)

    In this paper, we describe the use of the certification-trail technique as the basis of a hybrid framework for building formally verified software systems. Our technique involves formally verifying only a part of a software system; however, the technique yields a software system which still satisfies the most important correctness properties. Substantial savings in the overhead of software verific... View full abstract»

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  • Efficient hardware hashing functions for high performance computers

    Publication Year: 1997, Page(s):1378 - 1381
    Cited by:  Papers (87)  |  Patents (60)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (32 KB)

    Hashing is critical for high performance computer architecture. Hashing is used extensively in hardware applications, such as page tables, for address translation. Bit extraction and exclusive ORing hashing “methods” are two commonly used hashing functions for hardware applications. There is no study of the performance of these functions and no mention anywhere of the practical perform... View full abstract»

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  • Fault tolerant algorithms for broadcasting on the star graph network

    Publication Year: 1997, Page(s):1357 - 1362
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (108 KB)

    Fault tolerant algorithms are presented for broadcasting on the star graph. In our algorithm, fault tolerance is achieved by constructing an isomorphism of the star network, such that the faulty nodes minimally disrupt the message passing sequence. It is shown that, in the presence of r(1⩽r⩽k-2) faults, at most r extra steps are required by our algorithm to perform a one-to-all broadcastin... View full abstract»

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  • A comprehensive reconfiguration scheme for fault-tolerant VLSI/WSI array processors

    Publication Year: 1997, Page(s):1363 - 1371
    Cited by:  Papers (42)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (228 KB)

    This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switch... View full abstract»

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The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org