By Topic

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on

Issue 4 • Date Nov 1997

Filter Results

Displaying Results 1 - 14 of 14
  • Stress-induced parametric shift in plastic packaged devices

    Page(s): 458 - 462
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    In order to determine the shift in device characteristics due to stresses the die experiences during assembly, long channel NMOS and PMOS transistors (6.25×6.25 μm) were encapsulated in plastic quad flat packages (PQFPs) and the shifts in device parameters were monitored. Shifts as much as -5.3% in drain current (Idsat) were recorded for the NMOS devices, and +1.64% for PMOS devices. These shifts indicate a biaxial compressive stress level of some 60-87 MPa after plastic packaging. Die attach alone (prior to plastic encapsulation) results in a biaxial tensile stress in the range 35-55 MPa. Different mold compounds can exert different stress levels and accompanying device parameter shifts. Prolonged high temperature storage, leading to resin shrinkage, also affects device characteristics. Short channel submicron devices, typical of what is used in products, are expected to show little shift. Monitoring device parameter shift is a simple technique and is well suited for quantifying the stresses the die experiences in a plastic package View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Use of surface insulation resistance and contact angle measurements to characterize the interactions of three water soluble fluxes with FR-4 substrates

    Page(s): 443 - 451
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (192 KB)  

    Soldering flux chemistry and its interaction with the printed wiring board have been important reliability concerns for a number of years. Post Vietnam investigation of military hardware revealed corrosion in some areas. The test method most frequently used to assess the corrosion potential of flux residues is surface insulation resistance (SIR) testing. This paper gives some background on surface insulation resistance testing and reports on its application to three different water soluble fluxes. The appearance of surface dendrites is linked to test procedures that allowed water condensation on the board surface. Subsurface conductive anodic filament formation is associated with the use of fluxes which contained polyglycols. The use of contact angle measurements to assess the effect of the soldering flux residues on the board is demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Physical design and assembly process development of a multichip package containing a light emitting diode (LED) array die

    Page(s): 389 - 395
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (436 KB)  

    This paper presents the physical design concept and process developments to construct a small module containing a chip with an array of miniature light emitting diodes (LEDs) as well as the driver control circuitry for the LED array, The module is composed of a glass substrate consisting of a fanout pattern from the input/output (I/O) bond pads of the fine pitch solder bumped LED array chip. The fanout I/O pattern of the glass terminates on a 40 mil pitch ball grid array land pattern. The LED array chip is bonded face down on the glass and underencapsulated with an optically transparent underfill. All of the driver board circuitry is on a glob top plastic ball grid array (GTPBGA) package whose solder balls are reflow attached to the assembled glass substrate and underencapsulated to provide a finished display module. To implement the module concept, fine pitch (i.e. 80 μm) 90 Pb/10 Sn solder bump technology, fluxless flip chip bonding, thin optically transparent underencapsulation technology had to be developed, as well as the development of a multichip 384 I/O 40 mil pitch GTPBGA. The solder balls on the 384 I/O GTPBGA are 30 Pb/70 In. The assembly technology and underencapsulation technology for the assembly of the glass substrate containing the LED array chip and the 384 I/O GTPBGA also had to be developed View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Study on the pressurized underfill encapsulation of flip chips

    Page(s): 434 - 442
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (248 KB)  

    Flip-chip technology generally requires encapsulation of the solder joints to reduce the loads on such joints during thermal excursions. At present, the encapsulation process by dispensing constitutes the primary obstacle to widespread acceptance and implementation of flip-chip technology because of the long process times involved and the subsequent reliability and reparability problem. A new process to encapsulate flip-chips has been developed. This process uses a special mold to surround the chip to be encapsulated and injects the encapsulation material at elevated pressure. The experimental results show that the pressurized encapsulation process reduces the fill time (by as much as a factor of 1000), is able to perform the encapsulation at room temperature, fills the cavity completely without any voids and increases the capability of handling highly viscous encapsulants (1000 times more viscous than current commercial encapsulants) relative to the customary dispensing process for the particular case used in the current experiment View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-speed signal transmission at the front of a bookshelf packaging system

    Page(s): 353 - 360
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A front-connection technique using the front-side of the circuit board in rack systems configured like bookshelves is proposed to increase pin-counts for high-throughput switching modules (>20 Gb/s). This configuration technique was implemented using newly developed front connectors and flexible printed-circuit (FPC) cables that are both impedance-matched. This configuration enables the use of a new transmission route that meanders through every signal transmission line of every circuit board, backplane, and FPC cable. This route can extend the functional block size from the size of the circuit board to that of the unit, In a signal transmission experiment between circuit boards with this meander route passing through signal lines of an 18-cm-long FPC cable and over a distance of ten slots in the backplane, error-free (<10-11) signal transmission of 223-1 nonreturn-to-zero (NRZ) pseudo-random bit sequences (PRBS) at 622.08 Mb/s was obtained View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Optimization of high pin count cavity-up enhanced plastic ball grid array (EPBGA) packages for robust design

    Page(s): 376 - 388
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (500 KB)  

    Three-dimensional (3-D) nonlinear finite element models of epoxy encapsulated enhanced plastic ball grid array (EPBGA) packages with and without an aluminum lid have been developed using ANSYS finite element simulation code. The model has been used to optimize the packages for robust design and to determine design rules to keep package warpage within acceptable limits. An L18 Taguchi matrix has been developed to investigate the effect of die attach and encapsulant properties along with the substrate, encapsulant, die attach, and internal copper plane thicknesses on the reliability of the package during temperature cycling. For package failures, simulations performed represent temperature cycling from 165°C to -65°C. This condition is approximated by cooling the package mounted on a multilayer printed circuit board (PCB) from 165°C to -65°C. For coplanarity analysis, simulations have been performed without the PCB and the lowest temperature of the cycle is changed to 20°C. Predicted results indicate that for an optimum design, that is low stress in the package and low package warpage, encapsulant as well as die attach material should have low Young's modulus and low coefficient of thermal expansion. Furthermore, it is found that the substrate and the die attach epoxy thicknesses should be increased beyond the current design. In addition to the optimization analysis, plastic strain distribution on each solder ball has been determined to predict the location of the possible first solder ball failure View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Solder bump size and shape modeling and experimental validation

    Page(s): 452 - 457
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    Capillary physics was used to predict the size of solder bumps processed through a heated reflow cycle. Based on the density, surface tension, and volume of the solder material the effects of body forces are negligible compared to surface tension effects. For this case the predicted equilibrium shape of the molten solder is a truncated sphere, where the base of the sphere is defined by the bump input/output (I/O) pad on the integrated circuit (IC). Experiments using different size bumps on Si wafers were conducted to test the validity of the truncated sphere model. The experimental results matched the model to within 11% for the predicted height and 8% for the predicted radius. Using dimensionless variables for the solder volume, bump height, and bump radius allows these results for reflowed height and radius to each be plotted on a single curve and fitted with a single equation. These results can be used to design ICs, solder bumps, and solder bump assemblies in order to ensure that the attached IC can be underfilled reliably, and to ensure reliable products View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Rheological characterization of solder pastes for surface mount applications

    Page(s): 416 - 423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (168 KB)  

    Accurate rheological measurements are needed in order to correlate the rheological behavior of solder pastes to their performance in the surface mount technology (SMT) process. In this paper, we summarize our efforts to measure the rheological properties of solder pastes, and outline the difficulties in obtaining their true rheological properties. In particular, we show that the rheological measurements of solder pastes are affected by “slip” at the test-apparatus surfaces and by shear fracture within the sample which have not been taken into consideration heretofore View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analysis of the flow of encapsulant during underfill encapsulation of flip-chips

    Page(s): 424 - 433
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (352 KB)  

    In this paper, the flow of encapsulant during the underfill encapsulation of flip-chips has been studied. Analytical as well as numerical methods have been developed to analyze the flow. For capillary-driven encapsulation (by dispensing), the capillary force at the melt-front has been calculated based on a model for the melt-front shape. A model has also been developed for the analysis of forced-injection encapsulation. The numerical analysis uses a finite-element method based on a generalized Hele-Shaw method for solving the flow field. Experiments have been performed to investigate the flow behavior using actual chips and encapsulants. Short-shot runs have been performed to observe the melt-front advancement at different flow times. In addition, measurements have been made of the material properties of the encapsulant, namely its viscosity, curing kinetics and surface-tension coefficient. The experimental and simulation results have been compared in terms of the flow-front shapes and times at different fill fractions. Such comparisons indicate that the model developed in this study is adequate to approximately simulate the flow during encapsulation of flip chips View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Long lossy lines (L3) and their impact upon large chip performance

    Page(s): 361 - 375
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    The semiconductor industry expects the performance of microprocessors to continue at its current rate of improvement; i.e. clock rates should double every two to three years. This is a commendable goal but it is also fair to question whether this is an achievable goal. The fundamental problem is that as groundrules are reduced, the natural tendency is to make smaller conductor cross-sectional areas. The result is a high resistance line that exhibits slow wave propagation effects. This reduces the general performance expectations. As circuits become faster and denser on the chip, line delays become greater than expected. This problem is analyzed and potential chip and packaging solutions are offered. Clock rate predictions for various design and process options are made. A tactical recommendation to consider a total packaged electronics solution is presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Photonic packaging using laser/receiver arrays and flexible optical circuits

    Page(s): 409 - 415
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (148 KB)  

    Optoelectronic modules and multifiber optical connectors were successfully applied to intrasystem interconnection within a large telecommunication transmission terminal. The optoelectronic modules are 32-channel 850 nm vertical cavity surface emitting laser (VCSEL) and detector arrays packaged using multichip module technology system components include multimode silica optical fibers and silicon V-groove technology based multifiber optical connectors. The system architecture presented particularly difficult challenges for parallel optics because of complex cable assemblies required by the fan-out nature of the cables and the signal bifurcation needed to accomplish duplication, Nevertheless, the experiments completed demonstrate that parallel optics can dramatically increase the capacity of telecommunications equipment with no significant changes in system or physical architecture. The density of the optical modules and connectors clearly demonstrates that optical interconnection technology will be able to support the input/output (I/O) requirements of new generations of integrated circuit technology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of intermetallic compounds on the shear fatigue of Cu/63Sn-37Pb solder joints

    Page(s): 463 - 469
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (216 KB)  

    The effect of Cu-Sn intermetallic compounds (IMC) on the fatigue failure of solder joints has been studied by means of shear cycling. The samples consist of leadless ceramic chip carriers (LCCC) soldered onto FR-4 printed circuit boards (PCB), and are prepared by conventional reflow soldering using a 63Sn-37Pb solder paste and then aged at 150°C for 1, 4, 9, 16, 25, 36, and 49 days. The specimens are subjected to low cycle fatigue shear tests controlled by the displacement. The results indicate that the fatigue lifetime of the solder joints depends on the thickness of the LMC layer between the Cu-pad and bulk solder, and the quantitative relationship between the lifetime and thickness can be described as a monotonically decreasing curve. The greatest decrease is over the thickness range up to 2.8 μm, when the IMC/bulk solder interface becomes flat, corresponding to a lifetime decrease to 62% of the as assembled value. For further increase in IMC thickness the lifetime decreases more slowly. Evidently, the effect of the Cu-Sn intermetallic compounds on the joint fatigue lifetime is not only concerned with the IMC thickness hut also the interface morphology. A thick and flat LMC layer has a deleterious effect. The results of X-ray diffraction and metallographic analysis show that cracks initiate underneath the component metallization, and propagate along the IMC/solder interface, then toward the fillet. The Cu 3Sn (ε-phase) is formed between the Cu-pad and p-phase, and grows more quickly than the η-phase during storage and long term operation or aging tests. However, the Cu3Sn makes only a small direct contribution toward fatigue failure View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Effect of Au thickness on laser beam penetration in semiconductor laser packages

    Page(s): 396 - 402
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (176 KB)  

    Comprehensive measurements of the dependence of the weld width, penetration depth, and joint strength on the Au coating thickness in laser welding techniques for semiconductor laser packages are presented. The results obtained from the Invar-Invar joints show that the welded joints with thick Au coating exhibit narrower weld width, shallower penetration, and hence less joint strength than those the package joints with thin Au coating. A finite-element method (FEM) has been carried out on the effect of Au thickness on laser beam penetration in Invar-Invar joints. This method has been employed successfully to predict the laser beam penetration in laser welded Au-coated materials that the weld width and the penetration depth are reduced as the Au coating thickness increases. The likely cause for the reduction is the increased thermal conduction of thicker Au in the welded region. In addition to Au coating, the effect of Ni coating on laser beam penetration is also presented. Detailed knowledge of the effect of Au coating thickness on laser beam penetration is important for the practical design and fabrication of reliable optoelectronic packaging having laser welded Au-coated materials View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The packaging of large spot-size optoelectronic devices

    Page(s): 403 - 408
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (312 KB)  

    The demand for more bandwidth to the home is starting to drive optical fiber telecommunication systems further into the access network. For fiber systems to reach directly into customer premises the cost of the optoelectronic receivers and transmitters have to be significantly reduced. The major cost of producing these components is the active alignment step to couple an optical fiber to the semiconductor device. This paper details how by matching the output radiation pattern of the device to the input radiation pattern of an optical fiber low-cost passive alignments processes can be utilized View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

This Transaction ceased production in 1998. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope