By Topic

Computers, IEEE Transactions on

Issue 9 • Date Sep 1988

Filter Results

Displaying Results 1 - 21 of 21
  • Q-modules: internally clocked delay-insensitive modules

    Publication Year: 1988 , Page(s): 1005 - 1018
    Cited by:  Papers (62)  |  Patents (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1248 KB)  

    Q-modules are internally clocked modules that can be used to satisfy delay-insensitive specifications. A single delay element is required with a one-sided bound that its value be greater than the maximum delay of the combination logic. Prototypes of components to implement Q-modules have been designed, and a design aid program, QSYN, to place instances of these components, person... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Measuring parallelism in computation-intensive scientific/engineering applications

    Publication Year: 1988 , Page(s): 1088 - 1098
    Cited by:  Papers (24)  |  Patents (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (932 KB)  

    Describes COMET, (concurrency measurement tool), a software tool for measuring parallelism in large scientific/engineering applications. The proposed tool measures the total parallelism present in programs, filtering out the effects of communication/synchronization delays, finite storage, limited number of processors, the policies for management of processors and storage, etc. Although an ideal ma... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • On the construction of communication networks satisfying bounded fan-in of service ports

    Publication Year: 1988 , Page(s): 1148 - 1151
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (548 KB)  

    The problem of minimizing the number of service ports of a central facility which serves a number of users subject to some constraints is addressed. At any time, a set of at most s users may want to use the facility, and one user can be connected to each port at a given time. It is assumed that there are direct communication links from users to service ports, with at most d links... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design and analysis of dynamic redundancy networks

    Publication Year: 1988 , Page(s): 1019 - 1029
    Cited by:  Papers (6)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (960 KB)  

    The dynamic redundancy (DR) network is investigated in relation to fault-tolerant design for multistage interconnection network (MIN) based systems. The DR network can tolerate faults in the network and support a system to tolerate processing element (PE) faults without degradation by adding spare PEs, while retaining the full capability of a multistage cube network. A variation of the DR network,... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Test scheduling and control for VLSI built-in self-test

    Publication Year: 1988 , Page(s): 1099 - 1109
    Cited by:  Papers (73)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (992 KB)  

    The test scheduling problem for equal length and unequal length tests for VLSI circuits using built-in self-test (BIST) has been modeled. A hierarchical model for VLSI circuit testing is introduced. The test resource sharing model from C. Kime and K. Saluja (1982) is employed to exploit the potential parallelism. Based on this model, very efficient suboptimum algorithms are proposed for defining t... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modeling and measurement of error propagation in a multimodule computing system

    Publication Year: 1988 , Page(s): 1053 - 1066
    Cited by:  Papers (6)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1000 KB)  

    An error propagation model has been developed for multimodule computing systems in which the main parameters are the distribution functions of error propagation times. A digraph model is used to represent a multimodule computing system, and error propagation in the system is modeled by general distributions of error propagation times between all pairs of modules. Two algorithms are developed to co... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An incentive compatible flow control algorithm for rate allocation in computer networks

    Publication Year: 1988 , Page(s): 1067 - 1072
    Cited by:  Papers (4)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (464 KB)  

    The dynamic resource sharing that is a characteristic of store-and-forward computer/communication networks allows efficient use of the communication channel but may result in congestion and unfairness with high utilizations. A flow control algorithm is presented to prevent these effects by fairly allocating input rates to the users of the network. The allocation of rates is posed as an optimizatio... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Dynamic remapping of parallel computations with varying resource demands

    Publication Year: 1988 , Page(s): 1073 - 1087
    Cited by:  Papers (26)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1180 KB)  

    The issue of deciding when to invoke a global load remapping mechanism is studied. Such a decision policy must effectively weigh the costs of remapping against the performance benefits, and should be general enough to apply automatically to a wide range of computations. The authors propose a general mapping decision heuristic, then study its effectiveness and its anticipated behavior on two very d... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of crosspoint-irredundant PLAs using minimal number of control inputs

    Publication Year: 1988 , Page(s): 1130 - 1134
    Request Permissions | Click to expandAbstract | PDF file iconPDF (476 KB)  

    The problem of determining a minimal number of control inputs for converting a programmable logic array (PLA) with undetectable faults to crosspoint-irredundant PLA for testing has been formulated as a nonstandard set covering problem. By representing subsets of sets as cubes, this problem has been reformulated as familiar problems. It is noted that this result has significance because a crosspoin... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Spanning multiaccess channel hypercube computer interconnection

    Publication Year: 1988 , Page(s): 1137 - 1142
    Cited by:  Papers (15)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (548 KB)  

    A distributed computer system based on a hypercube topology is proposed, where multiaccess channels spanning all dimensional axes provide processor interconnection. The multiprocessor system can be built at relatively low cost by combining the recent advances in high-capacity channels available through fiber optics, and demand-assignment multiple-access protocols, creating a highly fault-tolerant ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An architecture for a video rate two-dimensional fast Fourier transform processor

    Publication Year: 1988 , Page(s): 1145 - 1148
    Cited by:  Papers (6)  |  Patents (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (496 KB)  

    A description of an architecture capable of computing two-dimensional fast Fourier transforms on a 256×256 pixel image at a rate of 30 images per second is presented. The architecture consists of a small number of basic building blocks which may be repeated to yield any desired performance. To achieve video rate performance, 16 butterfly processors, arranged as four coupled clusters of four ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Modular error detection for bit-serial multiplication

    Publication Year: 1988 , Page(s): 1043 - 1052
    Cited by:  Papers (9)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (800 KB)  

    Special-purpose architectures have been proposed to provide high processing rates for signal processing applications. These architectures use highly concurrent structures on VLSI circuits to achieve billions of multiply/add operations per second. Both serial-parallel and fully bit-serial multiplier elements have been proposed for highly concurrent signal processing arrays. Error detection can be a... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Variants of an improved carry look-ahead adder

    Publication Year: 1988 , Page(s): 1110 - 1113
    Cited by:  Papers (26)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (196 KB)  

    An improved variation on the carry look-ahead adder has been proposed by H. Ling (IBM J. Res. Develop., vol.25, p.156, May 1981). Ling's approach is based on the propagation of a composite term in place of the conventional look-ahead carry. This approach gives an adder that is faster and less expensive. In the present study, Ling's adder is introduced and described in a general manner in order to ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Estimating metrical change in fully connected mobile networks-a least upper bound on the worst case

    Publication Year: 1988 , Page(s): 1156 - 1162
    Request Permissions | Click to expandAbstract | PDF file iconPDF (532 KB)  

    A least upper bound is derived on the amount of adjustment of virtual token passing (VTP) time needed to assure collision-free access control in VTP networks (i.e. networks that use `time-out' or scheduling function-based access protocols) and in which nodes change their spatial configuration due to motion (although always stay within range and in line-of-sight of each other). Since the new bound ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An analysis of vector startup access delays

    Publication Year: 1988 , Page(s): 1134 - 1137
    Request Permissions | Click to expandAbstract | PDF file iconPDF (272 KB)  

    In a multiport memory access vector processor such as the CRAY X-MP, the numbering of section (lines) relative to bank numbering affects the delay characteristics of vector memory accesses. The author examines numberings which affect the vector startup delay. It has been shown previously that section numberings now associated with the X-MP-4 reduced the steady-state section delays of randomly conf... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Built-in checking of the correct self-test signature

    Publication Year: 1988 , Page(s): 1142 - 1145
    Cited by:  Papers (8)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (384 KB)  

    A procedure is described for determining the initial value of a single or multiple input signature register (used to compress responses in built-in testing) so that the final good-machine signature is always constant, e.g. all zeros. In this way, it is possible to determine if a fault has been detected by ORing the outputs of the register stages. Since the OR operation can be built-in, a single ob... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Linear sum codes for random access memories

    Publication Year: 1988 , Page(s): 1030 - 1042
    Cited by:  Papers (10)  |  Patents (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (972 KB)  

    Linear sum codes (LSCs) form a class of error control codes designed to provide on-chip error correction to semiconductor random access memories (RAMs). They use the natural addressing scheme found on RAMs to form and access codewords with a minimum of overhead. The authors formally define linear sum codes and examine some of their characteristics. Specifically, they examine their minimum distance... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A data compression technique for built-in self-test

    Publication Year: 1988 , Page(s): 1151 - 1156
    Cited by:  Papers (79)  |  Patents (47)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (588 KB)  

    A data compression technique called self-testable and error-propagating space compression is proposed and analyzed. Faults in a realization of Exclusive-OR and Exclusive-NOR gates are analyzed, and the use of these gates in the design of self-testing and error propagating space compressors is discussed. It is argued that the proposed data-compression technique reduce the hardware complexity in bui... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Simple relationships among moments of queue lengths in product form queueing networks

    Publication Year: 1988 , Page(s): 1125 - 1129
    Cited by:  Papers (7)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (396 KB)  

    Obtains simple relationships among partial derivatives and moments of mean queue lengths in product form queueing network models. It is shown that the mean value analysis equations can be used to obtain recursive expressions which make it possible to easily evaluate these moments in a mean value analysis type recursion. These results are also considered important in applications such as optimizati... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of self-checking iterative networks

    Publication Year: 1988 , Page(s): 1121 - 1125
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (428 KB)  

    The relevant definitions are given and a model of self-checking iterative network is presented. A general combinational circuit was developed that is totally self-checking and can detect an error on the input code lines and transmit the error to the output code lines. Thus, an error generated in a cell is transmitted from cell to cell until the last cell is reached. The error, and fault that gener... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient testing of optimal time adders

    Publication Year: 1988 , Page(s): 1113 - 1121
    Cited by:  Papers (18)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (796 KB)  

    Considers the design of two well-known optimal time adders: the carry look-ahead adder and the conditional sum adder. It is shown that 6 log2(n)-4 and 6 log2(n)+2 test patterns suffice to completely test the n-bit carry look-ahead adder and the n-bit conditional sum adder with respect to the single stuck-at fault model (for a given set of b... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org