By Topic

Electron Device Letters, IEEE

Issue 6 • Date June 1989

Filter Results

Displaying Results 1 - 13 of 13
  • Surface recombination current with a nonideality factor greater than 2

    Page(s): 242 - 244
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (290 KB)  

    It is shown both theoretically and experimentally that under inverted surface conditions the surface recombination current of a bipolar transistor has an exponential nonideality factor >2. The behavior of the surface recombination current follows closely that of the excess leakage current in stressed-self-aligned silicon bipolar transistors at forward bias.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • High-quality deposited gate oxide MOSFET's and the importance of surface preparation

    Page(s): 245 - 248
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (359 KB)  

    The fabrication and electrical characteristics of MOSFETs incorporating thin gate oxides deposited by a modified plasma-enhanced chemical-vapor-deposition (PECVD) process are reported. The gate oxide deposition and all subsequent steps were carried out at or below 400 degrees C. These results represent the first demonstration of near-thermal-gate oxide quality. MOSFETs fabricated using a low-temperature PECVD gate oxide process without requiring a high-temperature anneal. The ultimate performance of the deposited oxide devices is shown to be critically dependent on the degree of process induced microroughness of the starting silicon surface. Low-temperature effective mobility measurements are used to compare inversion-layer scattering mechanisms in these devices.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Lateral IMPATT diodes

    Page(s): 249 - 251
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (319 KB)  

    Conventional IMPATT diodes are the highest-power microwave semiconductor devices, but they are difficult to couple light into, challenging to integrate into monolithic circuits, to incorporate a third terminal, or to series combine. The lateral IMPATT diode is proposed as a solution to these problems. This device is planar and features contact and drift regions that are all adjacent to the wafer surface. Two types of fabrication schemes are discussed and pulsed RF power results, up to 17.4 GHz, are demonstrated. This device structure promises to be well suited for microwave, millimeter-wave, and electrooptic integrated circuits in which maximum power is required.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The effect of transients on hot carriers

    Page(s): 252 - 254
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (316 KB)  

    The influence of time-dependent voltages on hot-carrier generation in MOSFETS is studied by transient device simulation. For transient times down to the nanosecond range, no transient effects on hot-carrier formation and injection are found. This result is confirmed experimentally by substrate current measurements under various dynamic voltage conditions down to rise/fall times of 3 ns. This result has important consequences for the interpretation of dynamic stress data, since it means that device-related dynamic effects can be neglected in comparison with interface-related effects in transient ranges relevant to practical applications.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient coupling of optical fiber to silicon photodiode

    Page(s): 255 - 256
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (258 KB)  

    A technique to couple an optical fiber to a silicon p-n junction diode photodetector is described. Spin on glass is used to create an alignment sheath to receive the tapered end of an optical fiber, to stabilize the structure, and to eliminate the air gap between the fiber and the photodetector. By using an antireflective film, differential responsivity of 0.58 A/W at a wavelength of 810 nm has been measured. Dark leakage current is less than 10 nA/cm/sup 2/.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Selectively deposited nickel film for via filling

    Page(s): 257 - 259
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (292 KB)  

    A selective deposition process is used to fill vias in VLSI multilevel interconnection. Ni film is chosen as the via-filling material because of its compatibility with the underlying Al film. The vias are filled with a thin Pd film first and a thick Ni film. The deposited Ni film is uniform and smooth in the via regions. This film is not attacked by the plasma etch used in subsequent Al patterning; therefore, the design rule of overlapping the second metal on vias can be relaxed. The specific via resistance of this process is 4*10/sup -9/ Omega -cm/sup 2/. The via resistance increases about 30% after an exposure to 450 degrees C for 8 h.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Thin-base bipolar transistor fabrication using gas immersion laser doping

    Page(s): 260 - 263
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (339 KB)  

    Gas immersion laser doping (GILD) is used to fabricate the base and emitter regions of narrow-base n-p-n bipolar transistors. The GILD process is unique in that it allows simple fabrication of box-like impurity profiles which can be placed very accurately in the vertical dimension (+or-100 AA). Transistors with base widths ranging from 700 to 1200 AA and DC forward current gains greater than 50 are fabricated.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Ion-implanted GaAs/AlGaAs heterojunction FET's grown by MOCVD

    Page(s): 264 - 266
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (253 KB)  

    The successful fabrication of an ion-implanted GaAs/AlGaAs heterojunction FET device is discussed. Half-micrometer gate-length FET devices are fabricated by ion implantation into GaAs/AlGa heterostructures grown by metalorganic chemical vapor deposition (MOCVD) on 3-in-diameter GaAs substrates. The FET device exhibits a maximum extrinsic transconductance of 280 mS/mm with reduced transconductance variation over 2 V of gate bias. Excellent microwave performance is achieved with an f/sub t/ of 40 GHz, which is comparable to results obtained from 0.25- mu m gate GaAs MESFETs. The effects of ion implantation on the heterojunction and corresponding device characteristics are also discussed.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Subpicosecond InP/InGaAs heterostructure bipolar transistors

    Page(s): 267 - 269
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (257 KB)  

    Bipolar transistors with subpicosecond extrinsic delay are discussed. These InP/InGaAs heterostructure transistors show a unity-current-gain cutoff frequency f/sub $/T=165 GHz and maximum oscillation frequency f/sub MAX/=100 GHz at room temperature. The authors model shows that an f/sub $/T beyond 386 GHz is obtainable by further vertical scaling. Ring oscillators implemented with nonthreshold logic (NTL) and transistors having f/sub MAX/=71 GHz show a propagation delay of 14.7 ps and 5.4 mW average power consumption per stage.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Blanket LVD tungsten silicide technology for smart power applications

    Page(s): 270 - 273
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (396 KB)  

    A high-frequency power MOSFET structure fabricated using blanket deposited LPCVD (low-pressure chemical vapor deposition) WSi/sub 2/ gate and selectively deposited LPCVD tungsten source contact metallurgy is reported. A high-density power MOSFET technology suitable for smart power applications which simultaneously lowers the gate sheet resistance and source contact resistance is discussed. This technology was used to fabricate 30-V and 50-V power FETs with excellent high-frequency performances. The measured specific on-resistance R/sub sp/, specific input capacitance C/sub sp/, and switching times are among the lowest reported in the literature for any power FET structure in this reverse blocking voltage range.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Collector offset voltage of heterojunction bipolar transistors grown by molecular beam epitaxy

    Page(s): 274 - 276
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (231 KB)  

    The collector-emitter offset voltages of InAlAs/InGaAs heterojunction bipolar transistors grown by molecular-beam epitaxy are discussed. Both the difference between emitter and collector areas and electrical asymmetry between emitter and collector junctions in these mesa-isolated transistors account for the offset voltages observed. Devices exhibited offset voltages in the range of 50-300 mV, depending on the structures and device sizes. Several electrical and geometrical factors affecting the offset voltage are discussed in detail.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Spatial charge distribution in as-deposited and UV-illuminated gate-quality nitrogen-rich silicon nitride

    Page(s): 277 - 279
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (323 KB)  

    Gate-quality N-rich amorphous SiN/sub 1.6/:H films prepared by plasma-enhanced chemical vapor deposition (PECVD) at substrate temperatures of 250 and 400 degrees C are discussed. Films of different thicknesses t, ranging from 20 to 1100 nm, were obtained by varying the deposition time. The flat-band voltage shift was found to be proportional to t and t/sup 2/ before and after UV illumination, respectively. The linear dependence before illumination suggests a centroid of the positive charge located close to (within a region narrower than 20 nm of) the silicon/nitride interface. After UV illumination the distribution of the positive charge throughout the film is uniform. The bulk value of the positive photoinduced fixed charges is around 9*10/sup 16/ and 3*10/sup 16/cm/sup -3/ for N-rich films deposited at 250 and 400 degrees C, respectively.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A self-aligned retrograde twin-well structure with buried p/sup +/-layer

    Page(s): 280 - 282
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB)  

    The retrograde twin wells and buried p/sup +/ layer are fabricated by a single lithographic step using high-energy ion implantation. The retrograde n-well is self-aligned to the retrograde p-well regions. This simple process allows a scalable CMOS structure for the very tight n/sup +/-to-p/sup +/ spacing. It provides latch-up immunity at the 1.5- mu m n/sup +/-to-p/sup +/ spacing and good isolation characteristics without additional n- and p-channel stops.<> View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Amitava Chatterjee