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Design & Test of Computers, IEEE

Issue 4 • Date Oct.-Dec. 1997

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Displaying Results 1 - 9 of 9
  • A core-based system-to-silicon design methodology

    Publication Year: 1997 , Page(s): 36 - 41
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (69 KB)  

    Faced with the task of developing a complex 0.5-μm digital demodulator/decoder, Motorola engineers developed a new design process based on reusable cores. Incorporating design, logic synthesis, and placement-and-routing tools in an automated environment, this methodology greatly reduces cycle time for complex deep-submicron designs. View full abstract»

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  • Using partial isolation rings to test core-based designs

    Publication Year: 1997 , Page(s): 52 - 59
    Cited by:  Papers (27)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    A partial isolation ring provides the same fault coverage as a full isolation ring but avoids adding multiplexers on critical timing paths and reduces area overhead. The authors examine several partial isolation ring selection strategies that vary in computational complexity View full abstract»

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  • A flexible DSP core for embedded systems

    Publication Year: 1997 , Page(s): 60 - 68
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Cores currently available for ASIC design allow little customization. The authors have developed a parameterized and extensible DSP core that offers system engineers a great deal of flexibility in finding the optimum cost performance ratio for an application View full abstract»

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  • Interface design for core-based systems

    Publication Year: 1997 , Page(s): 42 - 51
    Cited by:  Papers (3)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    The authors propose the use of temporal abstraction in system-on-chip design and describe its benefits vis-a-vis traditional approaches. Their approach allows rapid integration of legacy cores to meet high-level system requirements View full abstract»

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  • Detecting and preventing measurement errors

    Publication Year: 1997 , Page(s): 78 - 86
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    Modern e-beam probers may be as convenient to use as oscilloscopes, but their measurements can be misleading or even erroneous. The author warns of potential problems and suggests ways to prevent and cure faulty readings View full abstract»

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  • Designing and verifying embedded microprocessors

    Publication Year: 1997 , Page(s): 87 - 94
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (100 KB)  

    Motorola's ColdFire products are a line of microprocessors targeting embedded-system applications such as computer peripherals (disk drives, laser printers, scanners).They originated from the same design group that produced the 680X0 general purpose microprocessors, whose target market was desktop computing applications. The ColdFire microprocessors, however, target the highly competitive embedded market, whose time-to-market and cost requirements are much more stringent. The ColdFire design team received a set of challenges quite different from those associated with the 680X0 line. They had to minimize test costs since the target selling price was an order of magnitude less than that of a desktop microprocessor. With no room for design errors, they had to put processes in place that detect errors early in the design flow and provide feedback for continuous improvement. A new methodology reduced new product cycle time to less than a year for the ColdFire products and provided improved techniques for integrating cores in new applications. In addition, it increased quality measurement capability and reduced test cost View full abstract»

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  • Introducing core-based system design

    Publication Year: 1997 , Page(s): 15 - 25
    Cited by:  Papers (86)  |  Patents (35)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    In recent years cores have captured the imagination of designers who understand the potential of using these cells like integrated circuits on a PC board in building on-chip systems. With a rich cell library of predesigned, preverified circuit blocks, cores provide an attractive means to import technology to a system integrator and differentiate products by leveraging intellectual property advantages. Most importantly, core use shortens the time to market for new system designs through design reuse. Practical implementation of this design scenario, however, is fraught with unresolved issues: design methods for building single-chip systems, challenges in test and sign-off for these systems, and intellectual property licensing, protection, and liability. Here, we examine the evolving design flow for microelectronic systems, the market for core cells, and the challenges in using core cells for design, integration, assembly, and test of onchip systems View full abstract»

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  • Core design and system-on-a-chip integration

    Publication Year: 1997 , Page(s): 26 - 35
    Cited by:  Papers (9)  |  Patents (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    IBM's experience with core-based designs provides insight into methodology, SOC design styles, core design trade-offs, and ASIC design processes. The authors describe a prototype cosimulation system developed for the PowerPC core and present SOC designs to illustrate their methods View full abstract»

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  • Testing core-based systems: a symbolic methodology

    Publication Year: 1997 , Page(s): 69 - 77
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (160 KB)  

    Because they must rely on vendor-provided test patterns, designers of core-based systems are forced to use expensive scan-based test techniques. The authors' alternative solution exploits the expressiveness of binary decision diagrams to provide test generation for the system and testability estimation and improvement of its components View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty