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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • Date May 1997

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Displaying Results 1 - 12 of 12
  • Routing for array-type FPGA's

    Publication Year: 1997, Page(s):506 - 518
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (399 KB)

    In this paper, the routing problem for two-dimensional (2-D) field programmable gate arrays of a Xilinx-like architecture is studied. We first propose an efficient one-step router that makes use of the main characteristics of the architecture. Then we propose an improved approach of coupling two greedy heuristics designed to avoid an undesired decaying effect, a dramatically degenerated router per... View full abstract»

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  • Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques

    Publication Year: 1997, Page(s):485 - 496
    Cited by:  Papers (43)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (404 KB)

    A mathematical model for lossy, multiconductor transmission lines is introduced to facilitate the efficient application of Krylov subspace order-reduction techniques to the analysis of linear networks with transmission line systems. The model is based on the use of Chebyshev polynomial expansions for the approximation of the spatial variation of the transmission-line voltages and currents. The exp... View full abstract»

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  • Behavior and testability preservation under the retiming transformation

    Publication Year: 1997, Page(s):528 - 543
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (400 KB)

    Recently, it has been shown that retiming has a very strong impact on the run time required for sequential, structural automatic test pattern generators (ATPG's), as well as the levels of fault coverage and fault efficiency attained. In this paper, we show that, for circuits with no hardware reset or a global reset state, retiming preserves testability with respect to a single stuck-at fault test ... View full abstract»

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  • A small-signal MOSFET model for radio frequency IC applications

    Publication Year: 1997, Page(s):437 - 447
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (396 KB)

    In this paper, we present a small-signal model for an integrated MOS transistor which takes into account the distributed nature of the gate structure. The y parameters are derived, as well as an equation for an equivalent current noise source at the output. The equivalent current noise source takes into account the thermal noise generated by the resistive gate. The modeling equations are of relati... View full abstract»

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  • Performance analysis and optimization of mixed asynchronous synchronous systems

    Publication Year: 1997, Page(s):473 - 484
    Cited by:  Papers (6)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (512 KB)

    This paper deals with the system-level performance analysis and optimization of a class of digital systems we call mixed asynchronous-synchronous systems. In such a system, each computation module is either synchronous or asynchronous. The communication among all of the modules is assumed to be data driven. In order to adequately describe the timing of such architectures, we introduce a graph mode... View full abstract»

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  • Interface finite-state machines: definition, minimization, and decomposition

    Publication Year: 1997, Page(s):497 - 505
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    There is a well-recognized need for accurate timing verification tools that account for the functional behavior of component interfaces, and thereby do not traverse false combinational and sequential paths. Such tools, however, are susceptible to an exponential increase in task complexity as the circuit size and functional complexity of components increase. The viability of accurate timing verifie... View full abstract»

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  • On designing universal logic blocks and their application to FPGA design

    Publication Year: 1997, Page(s):519 - 527
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (368 KB)

    We present a general methodology to determine the logic function of a programmable cell. It is based on the concept of universal logic gate (ULG) that is capable of being configured to a given set of functions. The cells studied here can be configured to the desired functionality by applying input permutation, negation, bridging or constant assignment, or output negation. One application of this t... View full abstract»

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  • LOCSTEP: a logic-simulation-based test generation procedure

    Publication Year: 1997, Page(s):544 - 554
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (352 KB)

    We present a method to generate test sequences that detect large numbers of faults (close to or higher than the number of faults that can be detected by deterministic methods) at a cost which is significantly lower than any existing test generation procedure. The generated sequences can be used alone or as prefixes of deterministic test sequences. To generate the sequences, we study the test seque... View full abstract»

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  • ProperTEST: a portable parallel test generator for sequential circuits

    Publication Year: 1997, Page(s):555 - 569
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (304 KB)

    Parallel algorithms developed for CAD problems today suffer from two important drawbacks. First, they are machine specific, and tend to perform poorly on architectures other than the one for they were designed. Second, the quality of results degrades significantly during parallel execution. In this paper, we address these two problems for an important CAD application: test generation for sequentia... View full abstract»

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  • Symbolic FSM traversals based on the transition relation

    Publication Year: 1997, Page(s):448 - 457
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    We define the new “exist” generalized cofactor and image restrictor, a Boolean operator that supports the distributivity of conjunction and existential quantification. It finds a major application in existentially quantified products, like the transition relations that describe the sequential behavior of synchronous sequential circuits. We prove that the “exist” cofactor ex... View full abstract»

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  • The transition matrix for linear circuits

    Publication Year: 1997, Page(s):427 - 436
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (328 KB)

    The state transition matrix Φ(t)=eAt plays an important role in the state variable analysis of linear time-invariant circuits. In this paper, we give a method to compute the equivalent matrix for a set of differential-algebraic equations. Specifically, the algorithm is illustrated for the modified nodal analysis (MNA). A benefit of using MNA formulation is that equation formulation ... View full abstract»

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  • A unified lower bound estimation technique for high-level synthesis

    Publication Year: 1997, Page(s):458 - 472
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (500 KB)

    The importance of effective lower bound estimation (LBE) techniques is well established in high-level synthesis (HLS) since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of the previous work has focused on LBE techniques that use very simple cost models which primaril... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu