By Topic

Solid-State Circuits, IEEE Journal of

Issue 9 • Date Sept. 1997

Filter Results

Displaying Results 1 - 25 of 26
  • Introduction To The 18th Annual IEEE GaAs IC Symposium Special Issue

    Page(s): 1307 - 1309
    Save to Project icon | Request Permissions | PDF file iconPDF (29 KB)  
    Freely Available from IEEE
  • Introduction to the 1996 Bipolar/BiCMOS Circuits and Technology Meeting Special Issue

    Page(s): 1410 - 1411
    Save to Project icon | Request Permissions | PDF file iconPDF (17 KB)  
    Freely Available from IEEE
  • An 11 GHz 3-V SiGe voltage controlled oscillator with integrated resonator

    Page(s): 1451 - 1454
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (104 KB)  

    A 10.5- to 11-GHz fully monolithic voltage controlled oscillator circuit implemented in a standard SiGe bipolar technology is presented. An oscillator phase noise of -78 to -87 dBc/Hz is achieved at 100-kHz offset. The tuning range is close to 5% with an on-chip varactor-tuned resonator and for a control voltage of 0 to 3 V. The circuit draws less than 8 mA from a 3-V supply including the reference branch bias current View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design

    Page(s): 1430 - 1439
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB)  

    Fully scalable, analytical HF noise parameter equations for bipolar transistors are presented and experimentally tested on high-speed Si and SiGe technologies. A technique for extracting the complete set of transistor noise parameters from Y parameter measurements only is developed and verified. Finally, the noise equations are coupled with scalable variants of the HICUM and SPICE-Gummel-Poon models and are employed in the design of tuned low noise amplifiers (LNA's) in the 1.9-, 2.4-,and 5.8-GHz bands View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 50-W low distortion GaAs MESFET for digital cellular base stations

    Page(s): 1402 - 1404
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (80 KB)  

    A 50-W low distortion GaAs MESFET for L-band has been successfully developed by optimizing chip design and adopting nearly class-B push-pull operation. The newly developed FET achieved a P1 dB of 47.1 dBm (51.3 W) with a linear gain (GL) of 13.1 dB and the maximum drain efficiency of 57% (f=1.5 GHz, VDS=10 V, IDS=3%Idss). A saturation output power of 47.3 dBm (53.7 W) has also been obtained. This is the highest output power reported so far of GaAs FETs considering an operation at nearly class B. In addition, the FETs exhibited both good linearity and distortion performances. The newly developed FETs will contribute to the improvement in performance of digital cellular base station systems View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • InP-HBT chip-set for 40-Gb/s fiber optical communication systems operational at 3 V

    Page(s): 1371 - 1383
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (448 KB)  

    A chip set for a 40 Gb/s fiber optical communication system has been designed and fabricated. On-wafer measurements have been performed to verify circuit operations. As far as available measurement capabilities show, all circuits are functionally fulfilling specifications for 10 Gb/s operation at less than or equal to 3 V supply voltage. During the design phase especially the influence of interconnects on signal integrity was investigated and the results were implemented for automatic extraction. All the circuits were operational after the first processing round. No redesign was necessary View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low-power, high-speed, current-feedback op-amp with a novel Class AB high current output stage

    Page(s): 1470 - 1474
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (112 KB)  

    A complementary bipolar low-power, high-speed, current-feedback operational amplifier is described. The amplifier incorporates a new Class AB output stage that enables high output current drive of 100 mA and large voltage swing within 1 V of the supply rails while operating at low quiescent current of 1.5 mA. The amplifier was fabricated in a junction-isolated complementary bipolar process with NPN/PNP ft of 4.5/3.8 GHz. The amplifier, configured for noninverting gain of two and 100-Ω load, provides 3-dB bandwidth of 110 MHz and 2-V pulse rise time of 7 ns View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A monolithic gallium arsenide interval timer IC with integrated PLL clock synthesis having 500-ps single shot resolution

    Page(s): 1350 - 1356
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (144 KB)  

    A gallium arsenide (GaAs) integrated circuit for measuring single shot time intervals with 500-ps resolution has been designed, fabricated, and tested. The circuit contains a 12-b counter that can be extended externally and control circuitry for the detection of multiple intervals. Options such as number of intervals, minimum interval time, and timing resolution are user programmable. The circuit employs a self-contained 2.0-GHz phase-locked loop (PLL) clock synthesizer with less than 5 ps rms jitter and a lock time of 2.5 μs. The circuit is packaged in a 14-mm2, 52-pin thermally enhanced plastic package and operates from a single +5-V supply. The nominal power dissipation is 2.8 W. The circuit is fabricated in a 0.6-μm gate length, enhancement/depletion GaAs MESFET process utilizing four layers of gold interconnect metallization. Inductors, capacitors, and thin film resistors can be fabricated in this process, enabling integrated analog circuitry. The die size is 3.28 by 3.15 mm. The circuit has applications in collision avoidance sensors, laser rangefinders, surveying, police radar, and test instrumentation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The MICROMIXER: a highly linear variant of the Gilbert mixer using a bisymmetric Class-AB input stage

    Page(s): 1412 - 1423
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB)  

    This paper outlines the basic theory of a development of the Gilbert mixer. The bipolar junction transistor (BJT) differential pair widely used as the RF input stage is replaced by a bisymmetric Class-AB topology based on translinear principles. It does not have inherent gain compression, affording a greatly extended signal capacity. The linearity of variants of the basic form is excellent, providing two-tone intermodulation intercepts as high as +30 dBm, without the expenditure of high bias currents. It can operate on supplies as low as 2.2 V, with a power consumption of under 5 mW. The input impedance of this mixer is accurately controllable (typically 50 Ω) and provides a true broadband match. The noise figure depends on design details and is generally not as low as in mixers specifically optimized for noise performance, although acceptable for many receiver applications. Inductively degenerated variants can be tuned to a narrowband match at microwave frequencies and provide full-mixing SSB noise figures as low as 6.5 dB, Practical realizations are in use in applications to 1.9 GHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 20-40 Gb/s 0.2-μm GaAs HEMT chip set for optical data receiver

    Page(s): 1384 - 1393
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (328 KB)  

    Using our 0.2-μm AlGaAs-GaAs-AlGaAs quantum well high electron mobility transistor (HEMT) technology, we have developed a chip set for 20-40 Gb/s fiber-optical digital transmission systems. In this paper we describe five receiver chips: a limiting amplifier with a differential gain of 17 dB and a 3 dB bandwidth of 29.3 GHz, a 40 Gb/s clock recovery, a data decision and a 1:4 demultiplexer, both for bit rates of more than 40 Gb/s, and a static 1:4 divider with operating frequencies up to 30 GHz. All presented chips were characterized on wafer with 50-Ω coplanar test probes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 150-V subscriber line interface circuit (SLIC) in a new BiCMOS/DMOS-technology

    Page(s): 1475 - 1480
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB)  

    The presented IC performs the high-voltage functions of an electronic central office subscriber line interface without the need for any transformers or relays. The challenges of subscriber line interface circuit (SLIC) integration stem from the combination of conflicting requirements: low impedance line feeding in a 150-V range, current sensing with 0.2% relative accuracy, and stability up to 200 nF loads, while operating in the harsh environment of the telephone line. The newly developed BiCMOS/DMOS process 170-V smart power technology (SPT 170) together with circuit techniques that strongly emphasize the physical device properties (e.g., buffers with DMOS outputs, n-type supply voltage switch, accuracy by polyresistors) yielded a very robust 30 mm2 SLIC. All transmission specifications are met without trimming View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 40-Gb/s ICs for future lightwave communications systems

    Page(s): 1363 - 1370
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (280 KB)  

    This paper describes the device, circuit design, and packaging technologies applicable to 40-Gb/s-class future lightwave communications systems. A 0.1-μm gate InAlAs-InGaAs high electron mobility transistors (HEMTs) with InP recess etch stopper was adopted mainly for IC fabrication. Fabricated ICs demonstrate excellent data-multiplexing, demultiplexing, and amplifying operation at 10 Gb/s View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A super-dynamic flip-flop circuit for broad-band applications up to 24 Gb/s utilizing production-level 0.2-μm GaAs MESFETs

    Page(s): 1357 - 1362
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (204 KB)  

    This paper describes a novel dynamic flip-flop (FF) circuit that can operate 30% faster than conventional clocked inverter-type FFs. A new wideband clock buffer is introduced to cover the FF operation range. An 8- to 24-Gb/s decision circuit and a 9- to 26-GHz 1/2 frequency divider were developed utilizing production-level 0.2-μm GaAs MESFET technology View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Temperature dependence of Q and inductance in spiral inductors fabricated in a silicon-germanium/BiCMOS technology

    Page(s): 1455 - 1459
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (120 KB)  

    The behavior of on-chip, planar, spiral inductors fabricated over a conductive silicon substrate has been characterized over the temperature range from -55°C to +125°C. Quality factor (Q) was observed to decrease with increasing temperature at low frequency and increase with increasing temperature at high frequency. Inductance was seen to vary little over the temperature and frequency range. A SPICE model that incorporated the temperature dependence of the inductor's parasitics was presented and shown to give excellent agreement with measured data over the full temperature and frequency range View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Understanding linearity in wireless communication amplifiers

    Page(s): 1310 - 1318
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (324 KB)  

    This paper investigates the linearity of active devices and amplifiers that have modulated input signals. We describe an implementation of a mathematical technique for calculating spectral regrowth due to the nonlinear amplification of modulated signals typically used in wireless communication systems. This technique only requires knowledge of the single-tone gain and phase data as a function of input power and can be applied to any modulated signal given (a) the device or amplifier characteristics do not change significantly over the bandwidth of the input signal and (b) the modulation frequencies are much less than the carrier frequency. Verification of the mathematical technique is presented using examples of measured and calculated spectra for π/4-differential quadrature phase shift keying (DQPSK) personal handy phone system (PHS) and code division multiple access (CDMA) Offset-QPSK personal communication system (PCS) modulation schemes. This calculation technique is essential in determining fundamental tradeoffs between device performance (linearity, output power, gain, and power-added efficiency) and device bias conditions and load impedance View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • 27-GHz bandwidth high-speed monolithic integrated optoelectronic photoreceiver consisting of a waveguide fed photodiode and an InAlAs/InGaAs-HFET traveling wave amplifier

    Page(s): 1394 - 1401
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (236 KB)  

    A monolithic integrated photoreceiver for 1.55-μm wavelength has been designed for operation in a 20-Gb/s synchronous digital hierarchy system (SDH/SONET), based on a new integration concept. The optoelectronic integrated circuit (OEIC) receiver combines a waveguide-integrated PIN-photodiode and a traveling wave amplifier in coplanar waveguide layout with four InAlAs/InGaAs/InP-HFETs (0.7-μm gate length). The receiver demonstrates a bandwidth of 27 GHz with a low frequency transimpedance of 40 dBΩ. This is, to our knowledge, the highest bandwidth ever reported for a monolithic integrated photoreceiver on InP. Furthermore, a receiver sensitivity of -12 dBm in the fiber (20 Gb/s, BER=10-9) and an overall optical input dynamic range of 27 dB is achieved. Optical time domain multiplex (TDM) system experiments of the receiver packaged in a module show an excellently shaped eye pattern for 20 Gb/s and an overall sensitivity of -30.5 dBm (BER=10-9) [including erbium doped fiber amplifiers (EDFA)] View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Integrated RF components in a SiGe bipolar technology

    Page(s): 1440 - 1445
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    Several components for the design of monolithic RF transceivers on silicon substrates are presented and discussed. They are integrated in a manufacturable analog SiGe bipolar technology without any significant process alterations. Spiral inductors have inductance values in the range of ~0.15-80 nH with typical maximum quality-factors (Qmax ) of 3-20. The Qmax's are highest if the doping concentration under the inductors is kept minimum. It is shown that the inductor area is an important parameter toward optimization of Qmax at a given frequency. The inductors can be represented in circuit design by a simple lumped-element model. MOS capacitors have Q's of ~20/f (GHz)/C(pF), metal-insulator-metal (MIM) capacitors reach Q's of ~80/f (GHz)/C(pF), and varactors with a 40% tuning range have Q's of ~70/f (GHz)/C(pF). Those devices can he modeled by using lumped elements as well. The accuracy of the modeling is verified by comparing the simulated and the measured high-frequency characteristics of a fully integrated, passive-element bandpass filter View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Highly integrated three-dimensional MMIC technology applied to novel masterslice GaAs- and Si-MMICs

    Page(s): 1334 - 1341
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (228 KB)  

    A novel three-dimensional (3-D) masterslice monolithic microwave integrated circuit (MMIC) is presented that significantly reduces turnaround time and cost for multifunction MMIC production. This MMIC incorporates an artificial ground metal for effective selection of master array elements on the wafer surface, resulting in various MMIC implementations on a master-arrayed footprint in association with thin polyimide and metal layers over it. Additionally, the 3-D miniature circuit components of less than 0.4 mm2 in size provide a very high integration level. To clearly show the advantages, a 20-GHz-band receiver MMIC was implemented on a master array with 6×3 array units including a total of 36 MESFETs in a 1.78×1.78 mm area. Details of the miniature circuit components and the design, closely related to the fabrication process, are also presented. The receiver MMIC exhibited a 19-dB conversion gain with an associated 6.5-dB noise figure from 17 to 24 GHz and an integration level four times higher than conventional planar MMICs. This technology promises about a 90% cost reduction for MMIC because it can be similarly applied to large-scale Si wafers with the aid of an artificial ground View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A highly integrated multifunction macro synthesizer chip (MMSC) for applications in 2-18 GHz synthesized sources

    Page(s): 1405 - 1409
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (136 KB)  

    A highly integrated monolithic microwave integrated circuit (MMIC) that acts as the core of the RF section of a synthesized source is developed using commercially available 0.2-μm pseudomorphic high electron mobility transistor (PHEMT) technology. Measured performance is shown up to 18 GHz. The same system architecture is able to produce synthesized output through 40 GHz with modifications of some critical building blocks of the chip. The chip performs all the frequency selection and tuning functions. It has more than 30 RF blocks integrated on an area of 4.27×4.68 mml. Some individual blocks operate through 40 GHz View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low glitch 14-b 100-MHz D/A converter

    Page(s): 1465 - 1469
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (152 KB)  

    A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high β n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-μm BiCMOS technology and exhibits a measured glitch energy of 0.5 pV·s (singlet). Settling time to within ±0.012% of the final value is ⩽20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (fCLK) of 10 MHz and an output frequency (fOUT) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09×4.09 mm including bond pads and electrostatic discharge (ESD) protection devices View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A GaAs HEMT MMIC chip set for automotive radar systems fabricated by optical stepper lithography

    Page(s): 1342 - 1349
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (220 KB)  

    A 77 GHz automotive radar system for collision avoidance and intelligent cruise control has recently gained interest because of its huge market potential. The questions of the optimum technological and system approaches leading to both low cost and high performance have not yet been finally answered. The approach to this problem reported here differs mainly in two aspects from the GaAs monolithic microwave integrated circuit (MMIC) solutions described earlier: (1) 0.12 μm gatelength pseudomorphic high electron mobility transistors (PHEMTs) are fabricated by optical stepper lithography, (2) a coplanar design is used. A fully passivated PHEMT MMIC fabrication process is reported with current-gain and power-gain cutoff frequencies exceeding 115 and 220 GHz, respectively. The design and performance of a chip set consisting of four different MMICs [voltage controlled oscillator (VCO), harmonic mixer, transmitter, receiver] are described. The great potential of this MMIC approach to meet all system requirements of an automotive radar sensor in a cost-effective and production-oriented way is shown. To our knowledge, this is the first demonstration of W-band coplanar multifunctional MMICs fabricated by optical stepper lithography View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • New insight into subharmonic oscillation mode of GaAs power amplifiers under severe output mismatch condition

    Page(s): 1319 - 1325
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    This paper provides new insight into the cause of subharmonic generation in GaAs MESFET power amplifiers under severe output mismatch conditions. A nonlinear modeling methodology is developed to identify the root cause of subharmonic oscillations and provides a means to implement circuit techniques to suppress this mode of oscillation without degrading the desired power amplifier performance. The primary mechanism for low-order subharmonics generated as a result of large signal drive and severe output mismatch is shown to be parametric. This modeling-based technique is enabled through the use of a time domain MESFET model which achieves excellent convergence by avoiding the discontinuity in high-order derivatives that is typical of implementations that use conditional functions. This technique provides the design engineer for the first time the ability to determine the large signal parametric stability of a power amplifier operating into a severe mismatch and implement circuit solutions prior to MMIC fabrication View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A low distortion bipolar mixer for low voltage direct up-conversion and high IF systems

    Page(s): 1446 - 1450
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (124 KB)  

    This paper describes the implementation of a low distortion mixer for direct up-conversion and high IF systems. A Gilbert cell with a low distortion transconductance constitutes the mixer core. A current feedback loop is used to linearize the transconductance stage, achieving an alternate channel leakage of -71 dBc with a power penalty of 15%. The mixer operates from 2.7 to 7.5 V of supply voltage and over a temperature range of -40 to 85°C. It provides -3 dBm output power while drawing 7.5 mW from a 3-V supply. The mixer is implemented in 1-μm BiCMOS for a global system for mobile communications (GSM) chip set View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design of high-power, high-efficiency 60-GHz MMICs using an improved nonlinear PHEMT model

    Page(s): 1326 - 1333
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (212 KB)  

    This work describes the design and nonlinear modeling of two V-band monolithic microwave integrated circuit (MMIC) power amplifiers using a nonlinear high electron mobility transistor (HEMT) model developed specifically for very short gate length pseudomorphic HEMTs (PHEMTs). Both circuits advance the state-of-the-art of V-band power MMIC performance. The first, a single-ended design, produced 293 mW of output power with a record 26% power-added efficiency (PAE) and 9.9 dB of power gain at 62.5 GHz when measured on-wafer. The second MMIC, a balanced design with on-chip input and output Lange couplers for power combining, generated a record 564 mW of output power (27.5 dBm) with 21% PAE and 9.8 dB power gain. The MMIC's are passivated, thinned to 2 mils, and down-biased to 4.5 V for high reliability space applications. These excellent first-pass MMIC results are attributed to the use of an optimized 0.1-/μm PHEMT cell structure and a design based on millimeter-wave on-wafer device characterization, together with a new and very accurate large signal analytical FET model developed for 0.1-/μm PHEMTs View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A 1.9-GHz Si-bipolar variable attenuator for PHS transmitter

    Page(s): 1424 - 1429
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (172 KB)  

    A 4-dB step 28-dB variable attenuator for 1.9 GHz personal handy-phone system (PHS) transmitter was fabricated using silicon bipolar technology with fT of 15 GHz. Step accuracy within 1.2 dB and total vector modulation error of less than 4% are realized for -15 dBm output. The attenuator consumes 21 mA with 2.7-V power supply and occupies 1.1 mm×0.5 mm View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan