Scheduled System Maintenance
On Saturday, October 21, single article sales and account management will be unavailable until 6 PM ET.
Notice: There is currently an issue with the citation download feature. Learn more.

IEEE Transactions on Computers

Issue 10 • Oct 1997

Filter Results

Displaying Results 1 - 11 of 11
  • Partial resolution in branch target buffers

    Publication Year: 1997, Page(s):1142 - 1145
    Cited by:  Papers (10)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (96 KB)

    Branch target buffers, or BTBs, are small caches for program branching information. Like data caches, addresses are divided into equivalence classes based on their low order bits. Unlike data caches, however, complete resolution of a single address from within an equivalence class is not required for correct execution. Substantial savings are therefore possible by employing partial resolution, usi... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Progressive retry for software failure recovery in message-passing applications

    Publication Year: 1997, Page(s):1137 - 1141
    Cited by:  Papers (11)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (52 KB)

    A method of execution retry for bypassing software faults in message-passing applications is described in this paper. Based on the techniques of checkpointing and message logging, we demonstrate the use of message replaying and message reordering as two mechanisms for achieving localized and fast recovery. The approach gradually increases the rollback distance and the number of affected processes ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An efficient sorting algorithm on the multi-mesh network

    Publication Year: 1997, Page(s):1132 - 1137
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (104 KB)

    The shear-sort algorithm on an SIMD mesh model requires 4√N+o(√N) time for sorting N elements arranged on a √N×√N mesh. In this paper, we present an algorithm for sorting N elements in time O(N1/4) on an SIMD multi-mesh architecture, thereby significantly improving the order of the time complexity. The multi-mesh architecture is built around n2 b... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • The reconfigurable ring of processors: fine-grain tree-structured computations

    Publication Year: 1997, Page(s):1119 - 1131
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (428 KB)

    We study fine-grain computation on the Reconfigurable Ring of Processors (RRP), a parallel architecture whose processing elements (PEs) are interconnected via a multiline reconfigurable bus, each of whose lines has one-packet width and can be configured, independently of other lines, to establish an arbitrary PE-to-PE connection. We present a “cooperative” message passing protocol that... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Analytical performance modeling of hierarchical mass storage systems

    Publication Year: 1997, Page(s):1103 - 1118
    Cited by:  Papers (8)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (460 KB)

    Mass storage systems are finding greater use in scientific computing research environments for retrieving and archiving the large volumes of data generated and manipulated by scientific computations. This paper presents a queuing network model that can be used to carry out capacity planning studies of hierarchical mass storage systems. Measurements taken on a Unitree mass storage system and a deta... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Multilevel optimization of pipelined caches

    Publication Year: 1997, Page(s):1093 - 1102
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    This paper formulates and shows how to solve the problem of selecting the cache size and depth of cache pipelining that maximizes the performance of a given instruction-set architecture. The solution combines trace-driven architectural simulations and the timing analysis of the physical implementation of the cache. Increasing cache size tends to improve performance but this improvement is limited ... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Resource placement in torus-based networks

    Publication Year: 1997, Page(s):1083 - 1092
    Cited by:  Papers (50)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (220 KB)

    This paper investigates methods to locate system resources, such as expensive hardware or software modules, to provide the most effective cost/performance trade-offs in a torus parallel machine. This paper contains some solutions to perfect distance-t and perfectiquasi-perfect j-adjacency placement in a k-ary n-cube and a torus using Lee distance error-correcting codes. It also presents generalize... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient VLSI layouts for homogeneous product networks

    Publication Year: 1997, Page(s):1070 - 1082
    Cited by:  Papers (18)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (336 KB)

    In this paper, we develop generalized methods to layout homogeneous product networks with any number of dimensions, and analyze their VLSI complexity by deriving upper and lower bounds on the area and maximum wire length. In the literature, lower bounds are generally obtained by computing lower bounds on the bisection width or the crossing number of the network being laid out. In this paper, we de... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A signed-digit architecture for residue to binary transformation

    Publication Year: 1997, Page(s):1146 - 1150
    Cited by:  Papers (23)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (116 KB)

    A residue to binary converter architecture based on the Chinese Remainder Theorem (CRT) is presented. This is achieved by introducing a general moduli set Sk Sk={2m-1, 22om+1, 221m+1, 222m+1,....,222km +1} for Residue Number System (RNS) applications. Residue to binary converter architectures based on moduli sets So<... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design principles for practical self-routing nonblocking switching networks with O(N·log N) bit-complexity

    Publication Year: 1997, Page(s):1057 - 1069
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (292 KB)

    Principles for designing practical self-routing nonblocking N×N circuit-switched connection networks with optimal θ(N·log N) hardware at the bit-level of complexity are described. The overall principles behind the architecture can be described as “Expand-Route-Contract”. A self-routing nonblocking network with w-bit wide datapaths can be achieved by expanding the dat... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A comment on “An analytical model for designing memory hierarchies”

    Publication Year: 1997
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (16 KB)

    In our paper, “An analytical model for designing memory hierarchies” (see ibid., vol. 45, no. 10, p. 180-1, 194 (1996)), we made the following statement: “Failing to apply a specific model of workload locality makes it impossible to provide an easily used, closed-form solution for the optimal cache configuration, and so the results from these papers have contained dependencies on... View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org