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IEE Proceedings - Computers and Digital Techniques

Issue 5 • Date Sep 1997

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Displaying Results 1 - 14 of 14
  • Increasing cache bandwidth using multiport caches for exploiting ILP in non-numerical code

    Publication Year: 1997, Page(s):295 - 303
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (956 KB)

    Modern microprocessors that exploit instruction-level parallelism (ILP) require higher data cache bandwidth than sequential machines, since at least the same number of cache references (or more due to speculative execution) must be made in fewer clock cycles. To support the required bandwidth, multiport caches have been proposed, allowing the execution of multiple load/store instructions in a sing... View full abstract»

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  • Variable ordering for ordered binary decision diagrams by a divide-and-conquer approach

    Publication Year: 1997, Page(s):261 - 266
    Cited by:  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (616 KB)

    An efficient variable ordering strategy for ordered binary decision diagrams (OBDD) based on interleaving the compacted clusters is proposed. The novelty of this method is to apply the divide and conquer approach to find a good variable ordering efficiently for circuits with a large number of I/Os. First, a given circuit is partitioned into a number of clusters according to the correlations among ... View full abstract»

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  • Predicting the complexity of large combinational circuits through symbolic spectral analysis of their functional specifications

    Publication Year: 1997, Page(s):343 - 347
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (492 KB)

    The use of symbolic data structures to store pseudo-Boolean (i.e. integer-valued) functions has proved to be extremely effective in handling both transform matrices and spectral representations of large Boolean functions. The authors propose a novel application of symbolic spectral analysis techniques to the prediction of the complexity of a combinational circuit. They present a symbolic formulati... View full abstract»

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  • Hardware/software partitioning of embedded systems with multiple hardware processes

    Publication Year: 1997, Page(s):285 - 294
    Cited by:  Papers (3)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (984 KB)

    COSYN is an hardware/software partitioning tool for embedded systems with multiple hardware processes. It produces a system hardware/software partition whilst satisfying system constraints, where feasible. COSYN uses a CIPN (coloured interpreted Petri net) to model systems, and to provide simulation data for the partitioning algorithm. The CIPN provides modelling capability for multiple processes ... View full abstract»

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  • Dynamic parity logging disk arrays for engineering database systems

    Publication Year: 1997, Page(s):255 - 260
    Cited by:  Papers (1)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (544 KB)

    RAID (redundant arrays of inexpensive disks) has gained much attention in the recent development of fast I/O systems. Of the five levels, the traditional mirrored disk array still provides the highest I/O rate for small `write' transfers. This is because the mirrored disk array does not have the `small write problem' which is found in other levels of RAID. The authors propose a novel RAID architec... View full abstract»

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  • Task tree scheduling onto linear arrays using tabu search

    Publication Year: 1997, Page(s):317 - 323
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (724 KB)

    Tabu search is a promising optimisation heuristic that has been successfully applied to the solution of many combinatorial optimisation problems, yielding optimal or near optimal results. An efficient algorithm based on tabu search is presented, designated as TASS, for the problem of scheduling a tree-like task graph (task tree) onto linear arrays of processors, with the aim of minimising the syst... View full abstract»

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  • DOORS: an object-oriented CAD system for high level synthesis

    Publication Year: 1997, Page(s):331 - 342
    Cited by:  Patents (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1128 KB)

    To expedite the design process of a complex system, it is required to view the system as interactions of complex subsystems which are not necessarily RTL components and synthesise the hardware from such a specification. In the paper, an automated design and synthesis environment called DOORS has been proposed that can accept a complex system specification at such a high level of abstraction and sy... View full abstract»

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  • Inversion of cellular automata iterations

    Publication Year: 1997, Page(s):279 - 284
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (668 KB)

    An algorithm for inverting an iteration of the one-dimensional cellular automaton is presented. The algorithm is based on the linear approximation of the updating function, and requires less than exponential time for particular classes of updating functions and seed values. For example, an n-cell cellular automaton based on the updating function CA30 can be inverted in O(n) time for certain seed v... View full abstract»

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  • Asymptotic properties of queuing networks

    Publication Year: 1997, Page(s):249 - 254
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (588 KB)

    A new approach to the analysis of asymptotic properties of closed queuing networks with both constant service rates and, in certain cases, load-dependent service rates is developed. The method is based on a decomposition of the generating function of the normalising constant into simpler node functions which are easily inverted term by term. An exact closed form is obtained for the normalising con... View full abstract»

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  • Effective and concurrent checkpointing and recovery in distributed systems

    Publication Year: 1997, Page(s):304 - 316
    Cited by:  Patents (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1456 KB)

    The paper presents an effective application-transparent checkpointing/rollback scheme for multiple processes that communicate via message passing in a distributed system. The authors first propose a checkpointing scheme that uses the unforced checkpointing strategy and dynamically varies checkpoint intervals with respect to the frequency of message sending to reduce process rollback propagation. A... View full abstract»

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  • Matrix method for solving multivalued logic differential equations

    Publication Year: 1997, Page(s):267 - 272
    Cited by:  Papers (3)  |  Patents (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (504 KB)

    A method to solve logic differential equations, i.e. equations containing logic derivatives of multivalued logic (MVL) functions (with k values) is proposed. An initial differential equation is represented by a system of k logic equations of k variables given as 0-polarity Reed-Muller canonical expansion. This system is solved by means of a truncated orthogonal transform algorithm View full abstract»

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  • GRASS: an efficient gate re-assignment algorithm for inverter minimisation in post technology mapping

    Publication Year: 1997, Page(s):348 - 352
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (520 KB)

    Technology mapping is an important task transforming a multi-level onto a set of library gates. Its primary goal is to achieve a realisable circuit which meets design constraints. Inverter pairs are generally inserted to all internal nodes of a network to increase the flexibility of mapping the subject network onto the library gates, but introducing inverter pairs may also increase the number of u... View full abstract»

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  • Priority assignment in distributed real-time databases using optimistic concurrency control

    Publication Year: 1997, Page(s):324 - 330
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (668 KB)

    In studies of distributed real-time database systems (DRTDBSs), it is always assumed that earliest deadline first (EDF) is employed as the CPU scheduling algorithm. However, purely using the (ultimate) deadline for priority assignment may not be suitable, because different kinds of transactions, such as global and local transactions, may exist in the system. To improve the performance, more sophis... View full abstract»

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  • Feasibility test for real-time communication using wormhole routing

    Publication Year: 1997, Page(s):273 - 278
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (648 KB)

    Real-time applications are becoming increasingly demanding in terms of the computational power and the I/O bandwidth required. Massively parallel computers using routing are the most promising architectures to deliver scalable computational power efficiently. It follows that real-time applications will want to take advantage of these architectures. However, before real-time applications can exploi... View full abstract»

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