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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 7 • Jul 1989

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Displaying Results 1 - 13 of 13
  • Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling

    Publication Year: 1989, Page(s):724 - 730
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (576 KB)

    A mobility curve for electrons in a MOSFET inversion charge layer is determined from measured drain current of transistors produced by a wide range of MOS technologies. A comparison between this mobility curve and previously published results shows that a truly universal mobility curve does not exist and only local universal mobility curves can be expected, i.e. unique mobility curves which are va... View full abstract»

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  • Modeling of the MOS transistor for high frequency analog design

    Publication Year: 1989, Page(s):713 - 723
    Cited by:  Papers (20)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (816 KB)

    A high-frequency (HF) small-signal model is presented that is capable of describing accurately the MOS transistor (in saturation) at frequencies beyond the cutoff frequency. The model is carefully compared to other models. It is shown how all the circuit elements of the model can be measured. This measurement method uses S-parameter measurements, computer-controlled calibration techniques... View full abstract»

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  • Switching network logic approach to sequential MOS circuit design

    Publication Year: 1989, Page(s):782 - 794
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    A novel, systematic approach to sequential MOS circuit design is described. The approach aims at minimizing the number of transistors needed to implement a given switching function. The techniques used are based on the switching network logic (SNL) approach, which was previously introduced as a systematic method of designing MOS combinational logic circuits. The authors extend the approach to sequ... View full abstract»

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  • Using statecharts for hardware description and synthesis

    Publication Year: 1989, Page(s):798 - 807
    Cited by:  Papers (72)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (772 KB)

    Statecharts have been proposed recently as a visual formalism for the behavioral description of complex systems. They extend classical state diagrams in several ways, while retaining their formality and visual nature. The authors argue that statecharts can be beneficially used as a behavioral hardware description language. They illustrate some of the main features of the approach, including: hiera... View full abstract»

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  • Threshold voltage for GaAs MESFET with a recoil-implanted channel profile

    Publication Year: 1989, Page(s):817 - 820
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (252 KB)

    Calculations of threshold voltages and their variations with respect to fluctuations in the substrate dopant density and the channel depth were performed for a recoil-implanted profile of a GaAs MESFET. It was observed that for these very shallow channels, the range of threshold voltages obtained was considerably smaller for different nitride thicknesses and there was a noticeable reduction in the... View full abstract»

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  • Algorithms for hardware allocation in data path synthesis

    Publication Year: 1989, Page(s):768 - 781
    Cited by:  Papers (149)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1224 KB)

    Novel algorithms for the simultaneous cost/resource-constrained allocation of registers, arithmetic units, and interconnect in a data path have been developed. The entire allocation process can be formulated as a two-dimensional placement problem of microinstructions in space and time. This formulation readily lends itself to the use of a variety of heuristics for solving the allocation problem. T... View full abstract»

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  • A totally self-checking checker for Borden's code

    Publication Year: 1989, Page(s):731 - 736
    Cited by:  Papers (11)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (456 KB)

    It is well known that a large number of errors in VLSI circuits are unidirectional in nature. J.M. Borden (Inf. Control, vol.53, p.66-73, April 1982) has studied a code for detecting only t, not all, unidirectional errors. For a code to be utilized in a self-checking system, a self-checking checker must exist for it. The totally self-checking (TSC) checker is one such checker. Many design... View full abstract»

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  • On empty rooms in floorplan graphics: comments on a deficiency in two papers

    Publication Year: 1989, Page(s):795 - 797
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (204 KB)

    Floorplan graphs are used in many placement and routing systems for VLSI building-block layout. S. Kimura et al.(ibid., vol. CAD-2, p.285-92, Oct. 1983) and W.M. Dai (ibid., vol.CAD-4, p.189-97, July 1985) proposed algorithms to construct such a graph from a geometrical placement of the building blocks and to define a channel structure from the floorplan graph. In the absence of empty rooms in the... View full abstract»

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  • Limitations of switch level analysis for bridging faults

    Publication Year: 1989, Page(s):807 - 811
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (496 KB)

    Switch-level models are widely used for fault analysis of MOS digital circuits. Switch-level analysis (SLA) provides significantly more accurate results compared to gate-level models, and also avoids the complexities of circuit-level analysis. The accuracy of SLA is critically examined, and conditions under which SLA may generate incorrect results are specified. Such conditions may occur when the ... View full abstract»

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  • Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation

    Publication Year: 1989, Page(s):737 - 743
    Cited by:  Papers (23)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (616 KB)

    An algorithmic framework is presented for mapping CMOS circuit diagrams into area-efficient, high-performance layouts in the style of one-dimensional transistor arrays. Using efficient search techniques and accurate evaluation methods, the huge solution space that is typical to such problems is transversed extremely fast, yielding designs of hand-layout quality. In addition to generating circuits ... View full abstract»

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  • Improved deterministic test pattern generation with applications to redundancy identification

    Publication Year: 1989, Page(s):811 - 816
    Cited by:  Papers (95)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (604 KB)

    The authors present several concepts and techniques aiming at a further improvement and acceleration of the deterministic test-pattern-generation and redundancy identification process. In particular, they describe an improved implication procedure and an improved unique sensitization procedure. While the improved implication procedure takes advantage of the dynamic application of a learning proced... View full abstract»

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  • Excellerator: custom CMOS leaf cell layout generator

    Publication Year: 1989, Page(s):744 - 755
    Cited by:  Papers (28)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1160 KB)

    A description is given of a program, Excellerator, which automatically generates full-custom symbolic CMOS cell layouts. The input is a transistor-level netlist with optimal constraints on layout shape and I/O port positions. The output is a high-quality virtual-grid-based layout suitable for use in a two-dimensional tiling methodology. I/O port locations can be optimized. Versatile support for di... View full abstract»

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  • Gate matrix partitioning

    Publication Year: 1989, Page(s):756 - 767
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (912 KB)

    An algorithm is presented which partitions a gate matrix into a number of matrices such that the total area and the aspect ratio of the circumscribing rectangle are improved. The algorithm is based on the min-cut algorithm. The gain function and the balance condition are redefined for the gate matrix problem. The time complexity of the algorithm is O(t)+O(|NI|2), whe... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu